pef20550 Infineon Technologies Corporation, pef20550 Datasheet - Page 79

• Manufacturer Part Number: pef20550
• Description: Extended Line Card Interface Controller Elic
• Manufacturer: Infineon Technologies Corporation

PEB 20550
PEF 20550
Functional Description
2.2.7.7 Serial Port Configuration
The SACCO supports different serial port configuration, enabling the use of the circuit in
– point-to-point configurations
– point-to-multi-point configurations
– multi master configurations
Point-to-Point Configuration
The SACCO transmits frames without collision detection/resolution.
(CCR1:SC1, SC0: 00)
Additionally the input CxD can be used as a "clear to send" strobe. Transmission is
inhibited by a "1" on the CxD-input. If "CxD" becomes "1" during the transmission of a
frame, the frame is aborted and IDLE is transmitted. The CxD-pin is evaluated with the
falling edge of HDC.
V
When the "clear to send" function is not needed, CxD must be tied to
.
SS
Bus Configuration
The SACCO can perform a bus access procedure and collision detection. As a result,
any number of HDLC-controllers can be assigned to one physical channel, where they
perform statistical multiplexing.
Collisions are detected by automatic comparison of each transmitted bit with the bit
received via the CxD input. For this purpose a logical AND of the bits transmitted by
parallel controllers is formed and connected to the input CxD. This may be implemented
most simply by defining the output line to be open drain. Consequently the logical AND
of the outputs is formed by simply tying them together ("wired or"). The result is returned
to the CxD-input of all parallel circuits.
When a mismatch between a transmitted bit and the bit on CxD is detected, the SACCO-
stops sending further data and IDLE is transmitted. As soon as it detects the transmit
bus to be idle again, the controller automatically attempts to re-transmit its frame. By
definition, the bus is assumed idle when x consecutive ones are detected in the transmit
channel. Normally x is equal to 8.
An automatic priority adjustment is implemented in the multi master mode. Thus, when
a complete frame is successfully transmitted, x is increased to 10, and its value is
restored to 8 when 10 '1's are detected on the bus (CxD). Furthermore, transmission of
new frames may be started by the controller after the 10
th
'1'.
This multi master, deterministic priority management ensures an equal right of access of
every HDLC-controller to the transmission medium, thereby avoiding blocking situations.
Semiconductor Group
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