pef20550 Infineon Technologies Corporation, pef20550 Datasheet - Page 78

• Manufacturer Part Number: pef20550
• Description: Extended Line Card Interface Controller Elic
• Manufacturer: Infineon Technologies Corporation

Clock Mode 3
In clock mode 3 SACCO-A is multiplexed among multiple subscribers under the control
of the D-channel arbiter. It must be used only in combination with transparent mode 0.
Serial data is transferred on (received from) the D-channels of the EPIC-1 IOM-2
interfaces. The data clock is derived from DCL. The D-channel arbiter generates the
receive and transmit strobes.
When bit CCR2:TXDE is set, the transmitted D-channel data can additionally be
monitored on pin TxDA delayed by 1 bit. The timing is identical to clock mode 1 assuming
a transmit strobe during the transmission of the third and fourth bit following the rising
FSC-edge.
Receive Status Byte in Clock Mode 3
In clock mode 3 the receive status byte is modified when it is copied into RFIFO. It
contains the following information:
VFR
RDO
CRC
CHAD4..0 Channel Address 4…0.
Note: The contents of the receive status register is not changed.
Semiconductor Group
bit 7
VFR
Valid Frame.
Indicates whether the received frame is valid (’1’) or not (’0’ invalid).
A frame is invalid when
– its length is not an integer multiple of 8 bits (n
– it is too short, depending on the selected operation mode (transparent
– the frame was aborted from the transmitting station.
Receive Data Overflow.
A '1' indicates, that a RFIFO-overflow has occurred within the actual frame.
CRC Compare Check.
0: CRC check failed, received frame contains errors.
1: CRC check o.k., received frame is error free.
CHAD4..0 identifies on with IOM-port/channel the corresponding frame was
received:
CHAD4..3: IOM-port number (3 - 0)
CHAD2..0: IOM-channel number (7 - 0)
RDO
mode 0: 2 bytes minimum),
CRC
CHAD4
78
CHAD3
CHAD2
8 bits), e.g. 25 bit,
Functional Description
CHAD1
PEB 20550
PEF 20550
bit 0
CHAD0
01.96