pef20550 Infineon Technologies Corporation, pef20550 Datasheet - Page 357

• Manufacturer Part Number: pef20550
• Description: Extended Line Card Interface Controller Elic
• Manufacturer: Infineon Technologies Corporation

6.1.2.1 EPIC
Configuration of the PCM interface: Set-up to meet the requirements of the switching
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Configuration of the CFI side: Set-up for IOM-2 subscribers
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6.1.2.2 SACCO-A Initialization
Initialization of SACCO-A for operation with D-channel Arbiter:
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Write
Reset SACCO-A:
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Read
Semiconductor Group
PMOD = 20
PBNR = FF
POFD = F1
POFU = 19
PCSR = 01
CMD1 = 20
CMD2 = D0
CBNR = FF
CTAR = 02
CBSR = 20
CSCR = 00
MODE = 98
CMDR = C1
ISTA_A= 10
CCR1 = 87
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Interface Initialization
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PCM mode 0, double rate clock (4 MHz, 2 Mbit/s), PFS
evaluated with falling edge of PDC
256 bits per PCM frame
with BPF = 256, the internal PFS marks downstream bit
number (BND) 2; for detail, refer to the Application
Hints, figure 62
the internal PFS marks upstream bit number (BNU) 2; for
detail, refer to the Application Hints, figure 62
no clock shift; PCM data sampled with falling, transmitted
with rising PDC
PDC and PFS used as clock and framing source for the CFI;
CRCL = PDC; prescaler divisor = 1; CFI mode 0
FSC shaped for IOM 2 interface; DCL = 2 x data rate;
CFI data received with falling, transmitted with rising CRCL
256 bits per CFI frame
PFS is to mark CFI time slot 0
PFS is to mark bit 7 of CFI time slot 0; no shift of CFI
upstream data relative to CFI downstream data
2 bit channels located in positions 7, 6 on all CFI ports
transparent mode 0; continuous frame transmission
switched ON; HDLC receiver active; test loop disabled
power up; point-to-point configuration. IDLE sequences as
interframe output; double rate data clock; clock mode 3
Receive Message Complete (RMC); Reset HDLC Receiver
(RHR); Transmitter Reset (XRES)
transmit pool ready
network (as for W&G PCM 4 measurement device)
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Application Notes
PEB 20550
PEF 20550
01.96