pef20550 Infineon Technologies Corporation, pef20550 Datasheet - Page 290

• Manufacturer Part Number: pef20550
• Description: Extended Line Card Interface Controller Elic
• Manufacturer: Infineon Technologies Corporation

Application hints: 1) If the D channel is idle and if it is required to transmit a 2 bit idle
Example
In CFI and PCM modes 0, CFI timeslots 10 and 11 of port 1 shall be initialized for central
D channel handling, the downstream D channel shall be switched from PCM port 0, TS5,
bits 5 … 4 and the upstream D channel shall be switched to PCM port 2, TS8, bits 3 … 2:
W:MADR
W:MAAR
W:MACR
W:MADR
W:MAAR
W:MACR
W:MADR
W:MAAR
W:MACR
Semiconductor Group
= 1100 0011
= 0010 1010
= 0111 1010
= 0001 0001
= 0010 1011
= 0111 0110
= 1111 1111
= 1010 1010
= 0111 1000
2) The central D channel scheme has primarily been designed to
code in the D channel (e.g. during the layer-1 activation or for
testing purposes), the 6 bit signaling handling scheme can be
selected for the downstream direction. The 2 D bits together with
the 4 C/I bits can then be written to via the even control memory
address. If the high impedance state is needed again, the
decentral D channel scheme has to be selected again.
switch the 16 kBit/s D channel to the PCM interface and to process
the C/I channel by the local P. For some applications however, it
is advantageous to switch the 2 D bits together with the 4 C/I bits
transparently to and from the PCM interface. The monitor channel
shall, however, still be handled by the internal MF handler. This
function might be useful if two layer-1 transceivers, operated in
“Repeater Mode”, shall be connected via a PCM link. For these
applications, the odd control memory address is written with the
64 kBit/s switching code ‘0001’, the CM data field pointing to the
desired PCM timeslot. Since also the MR and MX bits are being
switched, these must be carefully considered: in upstream
direction the two least significant bits of the PCM timeslot can be
set to high impedance via the tristate field; in downstream direction
the two least significant bits of the PCM timeslot must be received
at a logical 1 level since these bits will be logical ANDed at the CFI
with the downstream MR and MX bits generated by the MF
handler.
B
B
B
B
B
B
B
B
B
; C/I value ‘0000’
; downstream even TS, port 1 timeslot 10
; write CM code + data fields, CM code ‘1010’
; pointer to PCM port 0, TS5
; downstream odd TS, port 1 timeslot 11
; write CM code + data fields, CM code ‘0110’
; expected C/I value ‘1111’
; upstream even TS, port 1 timeslot 10
; write CM code + data fields, CM code ‘1000’
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Application Hints
PEB 20550
PEF 20550
01.96