MSC8103 Freescale Semiconductor / Motorola, MSC8103 Datasheet - Page 8

• Manufacturer Part Number: MSC8103
• Description: Network Digital Signal Processor
• Manufacturer: Freescale Semiconductor / Motorola

Signals/Connections
1.1 Power Signals
1.2 Clock Signals
1-4
V
V
V
V
GND
GND
GND
CLKIN
MODCK1
TC0
BNKSEL0
MODCK2
TC1
BNKSEL1
MODCK3
TC2
BNKSEL2
Power Name
Signal Name
DD
DDH
CCSYN
CCSYN1
SYN
SYN1
Internal Logic Power
V
an extremely low impedance path to the V
Input/Output Power
This source supplies power for the I/O buffers. The user must provide adequate external decoupling capacitors.
System PLL Power
V
should be provided with an extremely low impedance path to the V
SC140 PLL Power
V
with an extremely low impedance path to the V
System Ground
An isolated ground for the internal processing logic. This connection must be tied externally to all chip ground
connections, except GND
System PLL Ground
Ground dedicated for system PLL use. The connection should be provided with an extremely low-impedance path to
ground.
SC140 PLL Ground 1
Ground dedicated for SC140 core PLL use. The connection should be provided with an extremely low-impedance path
to ground.
Input
Input
Output
Output
Input
Output
Output
Input
Output
Output
DD
CC
CC
dedicated for use with the device core. The voltage should be well-regulated and the input should be provided with
dedicated for use with the system Phase Lock Loop (PLL). The voltage should be well-regulated and the input
dedicated for use with the SC140 core PLL. The voltage should be well-regulated and the input should be provided
Type
MSC8103 Network Digital Signal Processor, Rev. 12
Table 1-2.
Clock In
Primary clock input to the MSC8103 PLL.
Clock Mode Input 1
Defines the operating mode of internal clock circuits.
Transfer Code 0
Supplies information that can be useful for debugging bus transactions initiated by the MSC8103.
Bank Select 0
Selects the SDRAM bank when the MSC8103 is in 60x-compatible bus mode.
Clock Mode Input 2
Defines the operating mode of internal clock circuits.
Transfer Code 1
Supplies information that can be useful for debugging bus transactions initiated by the MSC8103.
Bank Select 1
Selects the SDRAM bank when the MSC8103 is in 60x-compatible bus mode.
Clock Mode Input 3
Defines the operating mode of internal clock circuits.
Transfer Code 2
Supplies information that can be useful for debugging bus transactions initiated by the MSC8103.
Bank Select 2
Selects the SDRAM bank when the MSC8103 is in 60x-compatible bus mode.
SYN
and GND
Table 1-3.
Power and Ground Signal Inputs
SYN1
DD
. The user must provide adequate external decoupling capacitors.
power rail.
CC
Clock Signals
power rail.
Description
Signal Description
CC
power rail.
Freescale Semiconductor