MSC8103 Freescale Semiconductor / Motorola, MSC8103 Datasheet - Page 52

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MSC8103

Manufacturer Part Number
MSC8103
Description
Network Digital Signal Processor
Manufacturer
Freescale Semiconductor / Motorola
Datasheet

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Physical and Electrical Specifications
2-12
Output (I/O)
Output (I/O)
PORESET
PORESET
HRESET
SRESET
Internal
Input
asserted for
CLKIN.
min 16
1
MSC8103 Network Digital Signal Processor, Rev. 12
Figure 2-7.
Any time
RSTCONF, HPE
HRM, BTM
pins are sampled
Reset Configuration
Host programs
2
Word
Host Reset Configuration Timing
PLL locked
PLL locks after
800 SPLLMFCLKs and
DLL locks 3073 BUS clocks
after PLL is locked.
When DLL is disabled,
reset period is shortened by
DLL lock time.
MODCK[1–3] pins
are sampled.
MODCK_H bits
are ready for PLL.
3
DLL locked
4
HRESET/SRESET are
extended for 512/515 BUS
clocks, respectively, from PLL
and DLL lock
5
6
Freescale Semiconductor

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