MSC8103 Freescale Semiconductor / Motorola, MSC8103 Datasheet - Page 22

• Manufacturer Part Number: MSC8103
• Description: Network Digital Signal Processor
• Manufacturer: Freescale Semiconductor / Motorola

Signals/Connections
1-18
Purpose I/O
General-
PA22
PA21
PA20
PA19
PA18
FCC1: TXD3
UTOPIA
FCC1: TXD4
UTOPIA
FCC1: TXD3
MII and HDLC nibble
FCC1: TXD5
UTOPIA
FCC1: TXD2
MII and HDLC nibble
FCC1: TXD6
UTOPIA
FCC1: TXD1
MII and HDLC nibble
FCC1: TXD7
UTOPIA
FCC1: TXD0
MII and HDLC nibble
FCC1: TXD
HDLC serial and transparent
Peripheral Controller:
Name
Dedicated Signal
Protocol
MSC8103 Network Digital Signal Processor, Rev. 12
Table 1-7.
Dedicated
Direction
I/O Data
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Port A Signals (Continued)
FCC1: UTOPIA Transmit Data Bit 3
The MSC8103 outputs ATM cell octets (UTOPIA interface data) on
TXD[0–7]. This is bit 3 of the transmit data. TXD7 is the most significant
bit. When no ATM data is available, idle cells are inserted. A cell is 53
bytes.
FCC1: UTOPIA Transmit Data Bit 4
The MSC8103 outputs ATM cell octets (UTOPIA interface data) on
TXD[0–7]. This is bit 4 of the transmit data. TXD7 is the most significant
bit. When no ATM data is available, idle cells are inserted. A cell is 53
bytes.
FCC1: MII and HDLC Nibble Transmit Data Bit 3
TXD[3–0] supports MII and HDLC nibble modes in FCC1. TXD3 is the
most significant bit.
FCC1: UTOPIA Transmit Data Bit 5
The MSC8103 outputs ATM cell octets (UTOPIA interface data) on
TXD[0–7]. This is bit 5 of the transmit data. TXD7 is the most significant
bit. When no ATM data is available, idle cells are inserted. A cell is 53
bytes.
FCC1: MII and HDLC Nibble Transmit Data Bit 2
TXD[3–0] is supported by MII and HDLC nibble modes in FCC1. This is
bit 2 of the transmit data. TXD3 is the most significant bit.
FCC1: UTOPIA Transmit Data Bit 6
The MSC8103MSC8103 outputs ATM cell octets (UTOPIA interface
data) on TXD[0–7]. This is bit 6 of the transmit data. TXD7 is the most
significant bit. When no ATM data is available, idle cells are inserted. A
cell is 53 bytes.
FCC1: MII and HDLC Nibble Transmit Data Bit 1
TXD[3–0] is supported by MII and HDLC transparent nibble modes in
FCC1. This is bit 1 of the transmit data. TXD3 is the most significant bit.
FCC1: UTOPIA Transmit Data Bit 7.
The MSC8103 outputs ATM cell octets (UTOPIA interface data) on
TXD[0–7]. TXD7 is the most significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes.
FCC1: MII and HDLC Nibble Transmit Data Bit 0
TXD[3–0] is supported by MII and HDLC nibble modes in FCC1. TXD0
is the least significant bit.
FCC1: HDLC Serial and Transparent Transmit Data Bit
This is the single transmit data bit in supported by HDLC serial and
transparent modes.
Description
Freescale Semiconductor