MSC8103 Freescale Semiconductor / Motorola, MSC8103 Datasheet - Page 100

• Manufacturer Part Number: MSC8103
• Description: Network Digital Signal Processor
• Manufacturer: Freescale Semiconductor / Motorola

Design Considerations
Select the bootstrap diodes such that a nominal V
V
series; each has a forward voltage (V
0.9 V on the 1.6 V power line. Once the core/PLL power supply stabilizes at 1.6 V, the bootstrap diodes will be
reverse biased with negligible leakage current. The V
processor. Do not use diodes with a nominal V
4.3 Power Considerations
The internal power dissipation consists of three components:
Power dissipation depends on the operating frequency of the different portions of the chip. Table 2-5 provides
typical power values at the specified operating frequencies. To determine the typical power dissipation for a given
set of frequencies, use the following equations:
Where:
• f
• f
• P
• All power numbers are in mW
• Power consumption is assumed to be linear with frequency. The first part of each equation computes a mw/MHz
To determine a total power dissipation in a specific application, you must add the power values derived from the
above set of equations to the value derived for I/O power consumption using the following equation for each output
pin:
Where: P = power in mW, C = load capacitance in pF, f = output switching frequency in MHz.
For an application in which external data memory is used in a 32-bit single bus mode and no other outputs are
active, the core runs at 200 MHz, the CPM runs at 100 MHz and the SIU runs at 50 MHz, power dissipation is
calculated as follows:
Assumptions:
• External data memory is accessed every second cycle with 10% of address pins switching.
• External data memory writes occurs once every eight cycles with 50% of data pins switching.
• Each address and data pin has a 30 pF total load at the pin.
• The application operates at
4-2
DD
MHz
in MHz
value that is then scaled based on the actual frequency used.
CORE
COREA
LCO
/
P
P
P
P
V
INT
CORE
CPM
SIU
CCSYN
, P
is the core frequency, f
= P
(f) = ((P
LSI
is the actual core frequency, F
(f) = ((P
(f) = ((P
power supply becomes active. In Figure 4-1, four MUR420 Schottky barrier diodes are connected in
CORE
, and P
SIU
CPM
+ P
CORE
LCP
– P
SIU
– P
are the leakage power values specified in Table 2-5
LSI
– P
+ P
LCP
)/f
LCO
CPM
V
SIU
)/f
DDH
SIU
MSC8103 Network Digital Signal Processor, Rev. 12
CPM
)/f
) × f
= 3.3 V.
CORE
is the SIU frequency, and f
F
) × f
SIUA
) of 0.6 V at high currents, so these diodes provide a 2.4 V drop, maintaining
P = C × V
SIUA
) × f
CPMA
+ P
COREA
is the actual SIU frequency, and F
LSI
F
+ P
that drops too low at high current.
DDH
DD
LCP
+ P
/V
2
F
× f × 10
CCSYN
should be effective at the current levels required by the
LCO
–3
is sourced from the
CPM
is the CPM frequency specified in Table 2-5 in
CPMA
V
DDH
is the actual CPM frequency
power supply until the
Freescale Semiconductor
Equation 2