MSC8103 Freescale Semiconductor / Motorola, MSC8103 Datasheet - Page 17

• Manufacturer Part Number: MSC8103
• Description: Network Digital Signal Processor
• Manufacturer: Freescale Semiconductor / Motorola

1.5 Memory Controller Signals
Refer to the memory controller chapter in the MSC8103 Reference Manual (MSC8103RM/D) for detailed
information about configuring these signals.
Freescale Semiconductor
IRQ7
INT_OUT
Notes:
CS[0–7]
BCTL1
BADDR[27–28]
ALE
BCTL0
PWE[0–7]
PSDDQM[0–7]
PBS[0–7]
Signal
Signal
1.
2.
3.
See the SIU chapter in the MSC8103 Reference Manual for details on how to configure these pins.
When used as the bus control arbiter for the system bus, the MSC8103 can support up to three external bus masters. Each
master uses its own set of Bus Request, Bus Grant, and Data Bus Grant signals (BR/BG/DBG,
EXT_BR2/EXT_BG2/EXT_DBG2, and EXT_BR3/EXT_BG3/EXT_DBG3). Each of these signal sets must be configured to
indicate whether the external master is or is not a MSC8103 master device. See the Bus Configuration Register (BCR)
description in the SIU chapter in the MSC8103 Reference Manual for details on how to configure these pins. The second and
third set of pins is defined by EXT_xxx to indicate that they can only be used with external master devices. The first set of pins
(BR/BG/DBG) have a dual function. When the MSC8103 is not the bus arbiter, these signals (BR/BG/DBG) are used by the
MSC8103 to obtain master control of the bus.
See the host interface (HDI16) chapter in the MSC8103 Reference Manual for details on how to configure these pins.
Input
Output
Data Flow
Data Flow
Output
Output
Output
Output
Output
Output
Output
Output
Table 1-5.
MSC8103 Network Digital Signal Processor, Rev. 12
Interrupt Request 7
One of eight external lines that can request a service routine, via the internal interrupt controller,
from the SC140 core.
Interrupt Output
Driven from the MSC8103 internal interrupt controller. Assertion of this output indicates that an
unmasked interrupt is pending in the MSC8103 internal interrupt controller.
Chip Select
Enable specific memory devices or peripherals connected to MSC8103 buses.
Buffer Control 1
Controls buffers on the data bus. Usually used with BCTL0. The exact function of this pin is defined
by the value of SIUMCR[BCTLC]. See the System Interface Unit (SIU) chapter in the MSC8103
Reference Manual for details.
Burst Address 27–28
Two of five outputs of the memory controller. These pins connect directly to memory devices
controlled by the MSC8103 memory controller.
Address Latch Enable
Controls the external address latch used in external master bus configuration.
Buffer Control 0
Controls buffers on the data bus. The exact function of this pin is defined by the value of
SIUMCR[BCTLC]. See the System Interface Unit (SIU) chapter in the MSC8103 Reference Manual
for details.
Bus Write Enable
Outputs of the bus General-Purpose Chip-select Machine (GPCM). These pins select byte lanes for
write operations.
Bus SDRAM DQM
Outputs of the SDRAM control machine. These pins select specific byte lanes of SDRAM devices.
Bus UPM Byte Select
Outputs of the User-Programmable Machine (UPM) in the memory controller. These pins select
specific byte lanes during memory operations. The timing of these pins is programmed in the UPM.
The actual driven value depends on the address and size of the transaction and the port size of the
accessed device.
System Bus, HDI16, and Interrupt Signals (Continued)
Table 1-6.
1
Memory Controller Signals
1
Description
Description
Memory Controller Signals
1-13