MSC8103 Freescale Semiconductor / Motorola, MSC8103 Datasheet - Page 47

• Manufacturer Part Number: MSC8103
• Description: Network Digital Signal Processor
• Manufacturer: Freescale Semiconductor / Motorola

2.6 AC Timings
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and
inputs. AC timings are based on a 50 pF load, except where noted otherwise, and 50 Ω transmission line.
2.6.1
2.6.2
Starting the device requires coordination among several input sequences including clocking, reset, and power.
Section 2.6.3 describes the clocking characteristics. Section 2.6.4 describes the reset and power-up characteristics.
You must use the following guidelines when starting up an MSC8103 device:
The following figures show acceptable start-up sequence examples. Figure 2-4 shows a sequence in which
V
nominal level and before
begins to toggle shortly before
Freescale Semiconductor
System Bus
Memory Controller
Parallel I/O
Note:
DDH
•
•
•
are raised together. Figure 2-5 shows a sequence in which
PORESET
for timing.
If possible, bring up the
the
CLKIN
guarantee correct device operation (see Figure 2-4 and Figure 2-6).
These are typical values at 65°C. The impedance may vary by ±25% depending on device process and operating temperature.
V
Output Buffer Impedances
Start-Up Timing
DDH
can start toggling after
levels and then the
and
Output Buffers
Figure 2-4.
TRST
o.5 V
1.6 V
2.2 V
3.3 V
V
DD
must be asserted externally for the duration of the power-up sequence. See Table 2-14
is applied. Figure 2-6 shows a sequence in which
V
MSC8103 Network Digital Signal Processor, Rev. 12
DD
V
DD
reaches the 0.5 V level.
Start-Up Sequence with V
PORESET/TRST Asserted
V
V
and
DD
Table 2-9.
V
DD
DDH
/V
CLKIN Starts Toggling
levels (see Figure 2-5 and Figure 2-6).
DDH
V
DDH
reaches its nominal level, but it must toggle before
Applied
levels together. For designs with separate power supplies, bring up
Output Buffer Impedances
V
V
DDH
DD
1
= Nominal Value
DD
= Nominal Value
CLKIN
and V
PORESET/TRST Deasserted
starts toggling after
DDH
Typical Impedance (Ω)
Raised Together
V
DD
V
V
DD
DDH
is raised after
35
35
55
Nominal Level
Time
Nominal Level
V
DDH
V
DD
reaches its
reaches 0.5 V to
V
DDH
AC Timings
and
V
DD
CLKIN
and
2-7