MSC8103 Freescale Semiconductor / Motorola, MSC8103 Datasheet - Page 20

• Manufacturer Part Number: MSC8103
• Description: Network Digital Signal Processor
• Manufacturer: Freescale Semiconductor / Motorola

Signals/Connections
1.6.1
1-16
Purpose I/O
General-
PA31
PA30
PA29
PA28
Port A Signals
FCC1: TXENB
UTOPIA master
FCC1: TXENB
UTOPIA slave
FCC1: COL
MII
FCC1: TXCLAV
UTOPIA slave
FCC1: TXCLAV
UTOPIA master, or
FCC1: TXCLAV0
UTOPIA master, Multi-PHY, direct
polling
FCC1: RTS
HDLC, Serial and Nibble
FCC1: CRS
MII
FCC1: TXSOC
UTOPIA master
FCC1: TX_ER
MII
FCC1: RXENB
UTOPIA master
FCC1: RXENB
UTOPIA slave
FCC1: TX_EN
MII
Peripheral Controller:
Name
Dedicated Signal
Protocol
MSC8103 Network Digital Signal Processor, Rev. 12
Table 1-7.
Dedicated
Direction
I/O Data
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
FCC1: UTOPIA Master Transmit Enable
Asserted by the MSC8103 (UTOPIA master PHY) when there is valid
transmit cell data (TXD[0–7]).
FCC1: UTOPIA Slave Transmit Enable
Asserted by an external UTOPIA master PHY when there is valid
transmit cell data (TXD[0–7]).
FCC1: Media Independent Interface Collision Detect
Asserted by an external fast Ethernet PHY when collision is detected.
FCC1: UTOPIA Slave Transmit Cell Available
Asserted by the MSC8103 (UTOPIA slave PHY) when the MSC8103
can accept one complete ATM cell.
FCC1: UTOPIA Master Transmit Cell Available
Asserted by an external UTOPIA slave PHY to indicate that it can accept
one complete ATM cell.
FCC1: UTOPIA Master Transmit Cell Available Multi-PHY Direct
Polling
Asserted by an external UTOPIA slave PHY using direct polling to
indicate that it can accept one complete ATM cell.
FCC1: Request To Send
In the standard modem interface signals supported by FCC1 (RTS,
CTS, and CD). RTS is asynchronous with the data. RTS is typically used
in conjunction with CD. The MSC8103 FCC1 transmitter requests the
receiver to send data by asserting RTS low. The request is accepted
when CTS is returned low.
FCC1: Media Independent Interface Carrier Sense
Asserted by an external fast Ethernet PHY to indicate activity on the
cable.
FCC1: UTOPIA Transmit Start of Cell
Asserted by the MSC8103 (UTOPIA master PHY) when TXD[0–7]
contains the first valid byte of the cell.
FCC1: Media Independent Interface Transmit Error
Asserted by the MSC8103 to force propagation of transmit errors.
FCC1: UTOPIA Master Receive Enable
Asserted by the MSC8103 (UTOPIA master PHY) to indicate that
RXD[0–7] and RXSOC are to be sampled at the end of the next cycle.
RXD[0–7] and RXSOC are enabled only in cycles following those with
RXENB asserted.
FCC1: UTOPIA Master Receive Enable
Asserted by an external PHY to indicate that RXD[0–7] and RXSOC is to
be sampled at the end of the next cycle. RXD[0–7] and RXSOC are
enabled only in cycles following those with RXENB asserted.
FCC1: Media Independent Interface Transmit Enable
Asserted by the MSC8103 when transmitting data.
Port A Signals
Description
Freescale Semiconductor