MSC8103 Freescale Semiconductor / Motorola, MSC8103 Datasheet - Page 11

• Manufacturer Part Number: MSC8103
• Description: Network Digital Signal Processor
• Manufacturer: Freescale Semiconductor / Motorola

Although there are eight interrupt request (
that can connect to these internal signal lines. After reset, the default configuration includes two
input lines. The designer must select one line for each required interrupt and reconfigure the other external signal
line or lines for alternate functions.
Freescale Semiconductor
A[0–31]
TT[0–4]
TSIZ[0–3]
TBST
IRQ1
GBL
Reserved
BADDR29
IRQ2
Reserved
BADDR30
IRQ3
Reserved
BADDR31
IRQ5
Signal
Input/Output
Input/Output
Input/Output
Input/Output
Input
Input/Output
Output
Output
Input
Output
Output
Input
Output
Output
Input
Data Flow
Table 1-5.
MSC8103 Network Digital Signal Processor, Rev. 12
Address Bus
When the MSC8103 is in external master bus mode, these pins function as the address bus. The
MSC8103 drives the address of its internal bus masters and responds to addresses generated by
external bus masters. When the MSC8103 is in Internal Master Bus mode, these pins are used as
address lines connected to memory devices and are controlled by the MSC8103 memory controller.
Bus Transfer Type
The bus master drives these pins during the address tenure to specify the type of transaction.
Transfer Size
The bus master drives these pins with a value indicating the number of bytes transferred in the
current transaction.
Bus Transfer Burst
The bus master asserts this pin to indicate that the current transaction is a burst transaction
(transfers four quad words).
Interrupt Request 1
One of eight external lines that can request a service routine, via the internal interrupt controller,
from the SC140 core.
Global
When a master within the chip initiates a bus transaction, it drives this pin. When an external master
initiates a bus transaction, it should drive this pin. Assertion of this pin indicates that the transfer is
global and it should be snooped by caches in the system.
The primary configuration is reserved.
Burst Address 29
One of five outputs of the memory controller. These pins connect directly to memory devices
controlled by the MSC8103 memory controller.
Interrupt Request 2
One of eight external lines that can request a service routine, via the internal interrupt controller,
from the SC140 core.
The primary configuration is reserved.
Burst Address 30
One of five outputs of the memory controller. These pins connect directly to memory devices
controlled by the MSC8103 memory controller.
Interrupt Request 3
One of eight external lines that can request a service routine, via the internal interrupt controller,
from the SC140 core.
The primary configuration is reserved.
Burst Address 31
One of five outputs of the memory controller. These pins connect directly to memory devices
controlled by the MSC8103 memory controller.
Interrupt Request 5
One of eight external lines that can request a service routine, via the internal interrupt controller,
from the SC140 core.
1
IRQ
System Bus, HDI16, and Interrupt Signals
) connections to the core processor, there are multiple external lines
1
1
1
1
1
1
1
Description
System Bus, HDI16, and Interrupt Signals
IRQ1
and two
IRQ7
1-7