MSC8103 Freescale Semiconductor / Motorola, MSC8103 Datasheet - Page 28

• Manufacturer Part Number: MSC8103
• Description: Network Digital Signal Processor
• Manufacturer: Freescale Semiconductor / Motorola

Signals/Connections
1.6.3
1-24
Purpose I/O
Purpose I/O
General-
General-
PB18
PC31
Port C Signals
FCC2: RXD3
MII and HDLC nibble
I
BRG1O
CLK1
TIMER1/2: TGATE1
2
C: SCL
Peripheral Controller:
Peripheral Controller:
Name
Name
Dedicated I/O
Dedicated I/O
Protocol
Protocol
MSC8103 Network Digital Signal Processor, Rev. 12
Table 1-8.
Dedicated
Table 1-9.
Direction
I/O Data
Input/Output
Dedicated
Direction
Output
I/O Data
Input
Input
Input
Port B Signals (Continued)
Baud-Rate Generator 1 Output
The CPM supports up to 8 BRGs used internally by the bank-of-clocks
selection logic and/or to provide an output to one of the 8 BRG pins.
BRG1O can be the internal input to the SIU timers. When CLK5 is selected
(see PC27 below), it is the source for BRG1O which is the default input for
the SIU timers. See the system interface unit (SIU) chapter in the
MSC8103 Reference Manual for additional information. If CLK5 is not
enabled, BRG1O uses an internal input. If TMCLK is enabled (see PC26
below), the BRG1O input to the SIU timers is disabled.
Clock 1
The CPM supports up to 10 clock input pins sent to the bank-of-clocks
selection logic, where they can be routed to the controllers.
Timer 1/2: Timer Gate 1
The timers can be gated/restarted by an external gate signal. There are
two gate signals: TGATE1 controls timer 1 and/or 2 and TGATE2 controls
timer 3 and/or 4.
FCC2: MII and HDLC Nibble Receive Data Bit 3
RXD3 is bit 3 and the most significant bit of the receive data nibble.
I
The I
clock (SDA). The I
that can connect several integrated circuits on a board. Clock rates run
up to 520 kHz@25 MHz system clock.
Port C Signals
2
C: Inter-Integrated Circuit Serial Clock
2
C interface comprises two signals: serial data (SDA) and serial
2
C controller uses a synchronous, multimaster bus
Description
Description
Freescale Semiconductor