MSC8103 Freescale Semiconductor / Motorola, MSC8103 Datasheet - Page 56

• Manufacturer Part Number: MSC8103
• Description: Network Digital Signal Processor
• Manufacturer: Freescale Semiconductor / Motorola

Physical and Electrical Specifications
2-16
Notes:
No.
31a
31b
31c
32a
32b
32c
33a
33b
35a
35b
35c
35d
34
36
TA delay from the 50% level of the DLLIN rising edge
•
•
TEA delay from the 50% level of the DLLIN rising edge
•
•
PSDVAL delay from the 50% level of the DLLIN rising edge
•
•
Address bus delay from the 50% level of the DLLIN rising edge
•
•
Address attributes: TT/TBST/TSIZ/GBL delay from the 50% level of the DLLIN rising edge
BADDR delay from the 50% level of the DLLIN rising edge
Data bus delay from the 50% level of the DLLIN rising edge
•
•
DP delay from the 50% level of the DLLIN rising edge
•
•
Memory controller signals/ALE delay from the 50% level of the DLLIN rising edge
DBG/BR/DBB delay from the 50% level of the DLLIN rising edge
AACK/ABB/CS delay from the 50% level of the DLLIN rising edge
BG delay from the 50% level of the DLLIN rising edge
TS delay from the 50% level of the DLLIN rising edge
Delay from the 50% level of the DLLIN rising edge for all other signals
1.
2.
Pipeline mode
Non-pipeline mode
Pipeline mode
Non-pipeline mode
Pipeline mode
Non-pipeline mode
Multi master mode (SIUBCR[EBM] = 1)
Single master mode (SIUBCR[EBM] = 0)
Pipeline mode
Non-pipeline mode
Pipeline mode
Non-pipeline mode
The maximum bus frequency depends on the mode:
• In 60x-compatible mode connected to another MSC8103 device, the frequency is determined by adding the input and output
longest timing values, which results in a frequency of 75 MHz for 30 pF output capacitance. In multi-master mode when
connected to another MSC8103 device, the frequency is determined by adding the input and output longest timing values,
which results in a frequency of 75 MHz for 30 pF output capacitance.
• Certain bus modes, such as non-extra cycle (EXDD = 1), non-pipelined, and ECC/Parity modes, result in slower bus
frequencies.
• In single-master mode, the frequency depends on the timing of the devices connected to the MSC8103.
Output specifications are measured from the 50% level of the rising edge of DLLIN to the 50% level of the signal. Timings are
measured at the pin.
MSC8103 Network Digital Signal Processor, Rev. 12
Characteristic
Table 2-17.
AC Timing for SIU Outputs
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
30 pF
5.0
4.0
3.0
3.5
4.0
3.5
6.3
5.5
5.5
3.5
5.0
6.0
4.0
6.5
5.5
4.0
4.5
4.0
3.5
4.5
Maximum
Freescale Semiconductor
50 pF
6.5
5.5
4.5
5.0
5.5
5.0
7.8
7.0
7.0
5.0
6.5
7.5
5.5
8.0
7.0
5.5
6.0
5.5
5.0
6.0
2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns