MSC8103 Freescale Semiconductor / Motorola, MSC8103 Datasheet - Page 65

• Manufacturer Part Number: MSC8103
• Description: Network Digital Signal Processor
• Manufacturer: Freescale Semiconductor / Motorola

Note: The timing values refer to minimum system timing requirements. Actual implementation requires
2.6.8
Freescale Semiconductor
No.
500
501
502
503
508
509
510
511
512
513
conformance to the specific protocol requirements. Refer to Chapter 1 to identify the specific input and
output signals associated with the referenced internal controllers and supported communication protocols.
For example, FCC1 supports ATM/Utopia operation in slave mode, multi-PHY master direct polling
mode, and multi-PHY master multiplexed polling mode and each of these modes supports its own set of
signals; the direction (input or output) of some of the shared signal names depends on the selected mode.
JTAG Signals
(Input)
TCK frequency of operation
TCK cycle time
TCK clock pulse width measured at 1.6 V
TCK rise and fall times
TMS, TDI data set-up time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO high impedance
TRST assert time
TRST set-up time to TCK low
TCK
PIO/TIMER/DMA outputs
PIO/TIMER/DMA inputs
Figure 2-23.
MSC8103 Network Digital Signal Processor, Rev. 12
503
Figure 2-24.
V
Characteristics
IH
DLLIN
Table 2-22.
V
PIO, Timer, and DMA Signal Diagram
IL
Test Clock Input Timing Diagram
22
V
502
M
JTAG Timing
501
23
503
42
502
V
M
100.0
Min
25.0
12.5
40.0
0.0
0.0
6.0
3.0
0.0
0.0
All frequencies
Max
40.0
15.0
20.0
3.0
—
—
—
—
—
—
AC Timings
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-25