MSC8103 Freescale Semiconductor / Motorola, MSC8103 Datasheet
MSC8103
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MSC8103 Summary of contents
Page 1
... DMA engine on a single device. With its four-ALU core, the MSC8103 can execute up to four multiply-accumulate (MAC) operations in a single clock cycle. The MSC8103 CPM is a 32-bit RISC-based communications protocol engine that can network to time-division multiplexed (TDM) highways, Ethernet, and asynchronous transfer mode (ATM) backbones ...
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... Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Signal/Symbol PIN PIN PIN PIN Note: Values for MSC8103 Network Digital Signal Processor, Rev Logic State True False True False , and V are defined by individual product specifications. OH pin is active RESET Signal State ...
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... Enhanced 16-bit parallel host interface (HDI16) — Supports a variety of microcontroller, microprocessor, and DSP bus interfaces • Phase-lock loops (PLLs) — System PLL — CPM DPLLs (SCC and SCM) • Process technology — 0.13 micron copper interconnect process technology MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor iii ...
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... Multi-channel modem banks • Multi-channel xDSL Product Documentation The documents listed in Table 1 are required for a complete description of the MSC8103 and are necessary to design properly with the part. Documentation is available from the following sources (see back cover for details): • A local Freescale distributor • ...
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... Signals/Connections The MSC8103 external signals are organized into functional groups, as shown in Table 1-1, Figure 1-1, and Figure 1-2. Table 1-1 lists the functional groups, states the number of signal connections in each group, and references the table that gives details on multiplexed signals within each group. Figure 1-1 shows MSC8103 external signals organized by function ...
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... RSTCONF BNK- TC[0–2] MODCK[1–3] SEL[0–2] THERM[1–2] SPARE1, SPARE5 Note: Refer to the System Interface Unit (SIU) chapter in the MSC8103 Reference Manual for details on how to configure these pins. MSC8103 Network Digital Signal Processor, Rev. 12 1-2 ↔ A[0–31] 32 ↔ TT[0–4] → 14 VDD 5 ↔ ...
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... RXADDR2/ RXADDR2 CD RXCLAV1 FCC2 CTS CD RXD RXADDR3 RXCLAV2 RTS/TENA TXADDR4 TXCLAV3 RXADDR4 RXCLAV3 RXPRTY TXPRTY TXADDR3 TXCLAV2 Figure 1-2. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor SI1 TDMA1 SMC2 Serial Nibble SMTXD L1TXD L1TXD0 SMRXD L1RXD L1RXD0 SMSYN L1TSYNC SCC2 L1RSYNC ...
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... Clock Mode Input 3 Defines the operating mode of internal clock circuits. TC2 Output Transfer Code 2 Supplies information that can be useful for debugging bus transactions initiated by the MSC8103. Bank Select 2 BNKSEL2 Output Selects the SDRAM bank when the MSC8103 is in 60x-compatible bus mode. ...
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... Input Enable Address Event Detection Channel 3 or generate one of the EOnCE events. Output The DSP has read the EOnCE Receive Register (ERCV). Triggers external debugging equipment. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor Reset, Configuration, and EOnCE Event Signals Table 1-3. ...
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... SRESET Input Soft Reset When asserted, this open-drain line causes the MSC8103 to enter the soft reset state. Note: See the emulation and debug chapter in the SC140 DSP Core Reference Manual for details on how to configure these pins. 1.4 System Bus, HDI16, and Interrupt Signals The system bus, HDI16, and interrupt signals are grouped together because they use a common set of signal lines ...
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... Input/Output Address Bus When the MSC8103 is in external master bus mode, these pins function as the address bus. The MSC8103 drives the address of its internal bus masters and responds to addresses generated by external bus masters. When the MSC8103 is in Internal Master Bus mode, these pins are used as address lines connected to memory devices and are controlled by the MSC8103 memory controller. TT[0– ...
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... DBG Input/Output Data Bus Grant Output An output when an internal arbiter is used. The MSC8103 asserts this pin as an output to grant data bus ownership to an external bus master. Input An input when an external arbiter is used. The external arbiter should assert this pin as an input to grant data bus ownership to the MSC8103 ...
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... When the HDI16 is programmed to interface with a double host request host bus, this pin is the transmit host request output (HTRQ/HTRQ). The signal can be programmed as driven or open drain. The polarity of the host request is programmable. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor System Bus, HDI16, and Interrupt Signals (Continued) ...
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... D[0–7]. EXT_BR2 Input External Bus Request 2 An external master asserts this pin to request bus ownership from the internal arbiter. MSC8103 Network Digital Signal Processor, Rev. 12 1-10 System Bus, HDI16, and Interrupt Signals (Continued) Description 3 3 ...
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... D[16–23]. EXT_DBG2 Output External Data Bus Grant 2 The MSC8103 asserts this pin to grant data bus ownership to an external bus master. IRQ3 Input Interrupt Request 3 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core ...
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... TEA Input/Output Transfer Error Acknowledge Indicates a bus error. masters within the MSC8103 monitor the state of this pin. The MSC8103 internal bus monitor can assert this pin if it identifies a bus transfer that is hung. NMI Input Non-Maskable Interrupt When an external device asserts this line, the MSC8103 NMI input is asserted ...
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... See the SIU chapter in the MSC8103 Reference Manual for details on how to configure these pins. 2. When used as the bus control arbiter for the system bus, the MSC8103 can support up to three external bus masters. Each master uses its own set of Bus Request, Bus Grant, and Data Bus Grant signals (BR/BG/DBG, EXT_BR2/EXT_BG2/EXT_DBG2, and EXT_BR3/EXT_BG3/EXT_DBG3) ...
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... UPM. PSDAMUX Output Bus SDRAM Address Multiplexer Controls the SDRAM address multiplexer when the MSC8103 is in External Master mode. PGPL5 Output Bus UPM General-Purpose Line 5 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM ...
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... The MSC8103 CPM supports the subset of MPC8260 signals as described below. • The MSC8103 CPM includes the following set of communication controllers: • Two full-duplex fast serial communications controllers (FCCs) that support: — Asynchronous transfer mode (ATM) through a UTOPIA 8 interface (FCC1 only)—The MSC8103 can operate as one of the following: UTOPIA slave device ° ...
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... Dedicated I/O Data Direction Output FCC1: UTOPIA Master Transmit Enable Asserted by the MSC8103 (UTOPIA master PHY) when there is valid transmit cell data (TXD[0–7]). Input FCC1: UTOPIA Slave Transmit Enable Asserted by an external UTOPIA master PHY when there is valid transmit cell data (TXD[0–7]). ...
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... I/O Data Direction Output FCC1: UTOPIA Receive Start of Cell Asserted by the MSC8103 (UTOPIA slave) for an external PHY when RXD[0–7] contains the first valid byte of the cell. Input FCC1: Media Independent Interface Receive Data Valid Asserted by an external fast Ethernet PHY to indicate that valid data is being sent ...
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... FCC1. This is bit 1 of the transmit data. TXD3 is the most significant bit. Output FCC1: UTOPIA Transmit Data Bit 7. The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0–7]. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. ...
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... This is bit 2 of the receive nibble data. RXD3 is the most significant bit. Input FCC1: UTOPIA Receive Data Bit 4. The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. RXD7 is the most significant bit. RXD0 is the least significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0– ...
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... SDMA transfer error registers. Input FCC1: UTOPIA RX Receive Data Bit 0 The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. RXD0 is the least significant bit of the receive data. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB is asserted ...
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... Port B Signals Dedicated I/O Data Direction Output FCC2: Media Independent Interface Transmit Error Asserted by the MSC8103 to force propagation of transmit errors. Input SCC2: Receive Data SCC2 receives serial data from RXD. Output Time-Division Multiplexing B2: Layer 1 Transmit Data TDMB2 transmits serial data out of L1TXD. ...
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... FCC2: Request to Send One of the standard modem interface signals supported by FCC2 (RTS, CTS, and CD). RTS is asynchronous with the data. RTS is typically used in conjunction with CD. The MSC8103 FCC2 transmitter requests the receiver to send data by asserting RTS low. The request is accepted when CTS is returned low. ...
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... L1TXD2 is bit 2 of the transmit data nibble. Input Time-Division Multiplexing D2: Layer 1 Transmit Synchronize Data The synchronizing signal for the transmit channel. See the Serial Interface with Time-Slot Assigner chapter in the MSC8103 Reference Manual. Input FCC2: MII and HDLC Nibble: Receive Data Bit 1 RXD1 is bit 1 of the receive data nibble ...
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... PC27 below the source for BRG1O which is the default input for the SIU timers. See the system interface unit (SIU) chapter in the MSC8103 Reference Manual for additional information. If CLK5 is not enabled, BRG1O uses an internal input. If TMCLK is enabled (see PC26 below), the BRG1O input to the SIU timers is disabled ...
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... Asserts an internal request to the CPM processor. The signal can be programmed as level- or edge-sensitive, and also has programmable priority. Refer to the RISC Controller Configuration Register (RCCR) description in the Chapter 17 of the MSC8103 Reference Manual for programming information. There are no current microcode applications for this request line reserved for future development. ...
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... Clock 5 When selected, CLK5 is a source for the SIU timers via BRG1O. See the System Interface Unit (SIU) chapter in the MSC8103 Reference Manual for additional information. If CLK5 is not enabled, BRG1O uses an internal input. If TMCLK is enabled (see PC26 below), the BRG1O input to the SIU timers is disabled ...
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... Timer Clock When selected, TMCLK is the designated input to the SIU timers. When TMCLK is configured as the input to the SIU timers, the BRG1O input is disabled. See the System Interface Unit (SIU) chapter in the MSC8103 Reference Manual for additional information. Output Baud-Rate Generator 7 Output The CPM supports BRGs used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins ...
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... The signal can be programmed as level- or edge-sensitive, and also has programmable priority. Refer to the RISC controller configuration register (RCCR) description in the Chapter 17 of the MSC8103 Reference Manual for programming information. There are no current microcode applications for this request line reserved for future development. ...
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... Direction Output Serial Interface 1: Layer 1 Strobe 1 The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture ...
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... These strobes can also generate output wave forms for such applications as stepper-motor control. Input SCC2: Carrier Detect, Request Enable Typically used in conjunction with RTS supported by SCC2. The MSC8103 SCC2 transmitter requests to the receiver that it sends data by asserting RTS low. The request is accepted when CTS is returned low. Output FCC1: UTOPIA Multi-PHY Master Receive Address Bit 1 This is master receive address bit 1 ...
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... ATM cell. Output Serial Interface 2: Layer 1 Strobe 2 The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture ...
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... Output Serial Interface 2: Layer 1 Strobe 4 The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture ...
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... PIO ports. Output SCC1: Request to Send, Transmit Enable Typically used in conjunction with CD supported by SCC2. The MSC8103 SCC1 transmitter requests the receiver to send data by asserting RTS low. The request is accepted when CTS is returned low. TENA is the signal used in Ethernet mode. Output FCC1: UTOPIA Multi-PHY Master Receive Address Bit 3 This is master receive address bit 3 ...
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... PC27 above the source for BRG1O which is the default input for the SIU timers. See the system interface unit (SIU) chapter in the MSC8103 Reference Manual for additional information. If CLK5 is not enabled, BRG1O uses an internal input. If TMCLK is enabled (see PC26 above), the BRG1O input to the SIU timers is disabled ...
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... Port D Signals (Continued) Dedicated I/O Data Direction Output Baud Rate Generator 2 Output The CPM supports BRGs for use internally to the MSC8103 and/or to provide an output to one of the 8 BRG pins. Input FCC1: UTOPIA Receive Parity This is the odd parity bit for RXD[0–7]. Input/ Output ...
Page 40
... Signals/Connections 1.7 JTAG Test Access Port Signals The MSC8103 supports the standard set of Test Access Port (TAP) signals defined by IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture specification and described in Table 1-11. Table 1-11. Signal Name Type TCK Input Test Clock A test clock signal for synchronizing JTAG test logic. ...
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... Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. Table 2-1 describes the maximum electrical ratings for the MSC8103. Rating ...
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... Table 2-2 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed. Table 2-2. Rating SC140 core supply voltage PLL supply voltage I/O supply voltage Input voltage Operating temperature range 2.3 Thermal Characteristics Table 2-3 describes thermal characteristics of the MSC8103. Characteristic 1, 2 Junction-to-ambient, single-layer board 1, 3 Junction-to-ambient, four-layer board 3 Junction-to-board 4 Junction-to-case Notes: 1 ...
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... DC Electrical Characteristics This section describes the DC electrical characteristics for the MSC8103. The measurements in Table 2-4 assume the following system conditions: • – 100 °C J • = 1.6 V ± • = 3.3 V ± DDH • GND DC Note: The leakage current is measured for nominal ...
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... Serial Communication Controller Clock Frequency (SCLK) Baud Rate Generator Clock Frequency (BRGCLK) External Clock Output Frequency (CLKOUT) Six bit values map the MSC8103 clocks to one of the valid configuration mode options. Each option determines the , SC140, system bus, SCC clock, CPM, and CLKIN dedicated input pins ( ) and three bits from the hard reset configuration word (MODCK_H) ...
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... System Clock Control Register Bit Type Reset Bit Type Reset Figure 2-2. SCCR is memory-mapped into the SIU register map of the MSC8103. Defaults Name Bit No. PORESET Hard Reset — — — 0–26 CLKODIS 0 Unaffected 27 — — — 28–29 DFBRG ...
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... Pins — — — 26–27 COREDF Configuration Unaffected 28–31 Pins MSC8103 Network Digital Signal Processor, Rev. 12 2-6 Table 2-8. SCMR Field Descriptions Description Core PLL Pre-Division Factor Core Multiplication Factor 60x-compatible Bus Division Factor CPM Division Factor SPLL Pre-Division Factor SPLL Multiplication Factor ...
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... Start-Up Timing Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.6.3 describes the clocking characteristics. Section 2.6.4 describes the reset and power-up characteristics. You must use the following guidelines when starting up an MSC8103 device: • and must be asserted externally for the duration of the power-up sequence ...
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... Delay between CLKOUT and DLLIN Notes: 1. Low CLKIN frequency causes poor PLL performance. Choose a CLKIN frequency high enough to keep the frequency after the predivider (SPLLMFCLK) higher than 18 MHz. CLKIN should have a 50% ± 5% duty cycle. 2. MSC8103 Network Digital Signal Processor, Rev applied DD ...
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... PORESET initiates the power-on reset flow that resets all the MSC8103s and configures various attributes of the MSC8103, including its clock mode. The MSC8103 can detect an external assertion of HRESET only if it occurs while the MSC8103 is not asserting reset. During HRESET, SRESET is asserted. HRESET is an open- drain pin ...
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... PORESET least 16 input clock cycles after external power to the MSC8103 reaches at least 2/3 V MSC8103 has five configuration pins, four of which are multiplexed with the SC140 EONCE Event ( ) pins and the fifth of which is the EE[4–5] addition to these configuration pins, three ( pins and the MODCK_H value in the Hard Reset Configuration Word determine the PLL locking mode, by defining the ratio between the DSP clock, the bus clocks, and the CPM clock frequencies ...
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... Host Reset Configuration Register address to program the reset configuration word, which is 32 bits wide. For more information, see the MSC8103 Reference Manual. The reset configuration word is programmed before the internal PLL and DLL in the MSC8103 are locked. The host must program it after the rising edge of the input ...
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... Input min 16 CLKIN. PORESET Internal HRESET Output (I/O) SRESET Output (I/O) Figure 2-7. MSC8103 Network Digital Signal Processor, Rev. 12 2-12 RSTCONF, HPE HRM, BTM pins are sampled Any time MODCK[1–3] pins are sampled. Host programs MODCK_H bits Reset Configuration are ready for PLL. ...
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... MODCK_H taken from the Reset Configuration Word. SPLL locking time is 800 reference clocks, which is the clock at the output of the SPLL Pre-divider. After the SPLL is locked, all the clocks to the MSC8103 are enabled. If the DLLDIS bit in the reset configuration word is reset, the DLL starts the locking process after the SPLL is locked ...
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... Physical and Electrical Specifications 2.6.5 System Bus Access Timing 2.6.5.1 Core Data Transfers Generally, all MSC8103 bus and system output signals are driven from the rising edge of the reference clock (REFCLK), which is . Memory controller signals, however, trigger on four points within a DLLIN cycle. DLLIN Each cycle is divided by four internal ticks: T1, T2, T3, and T4 ...
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... The set-up time for these signals is for synchronous operation. Any set-up time can be used for asynchronous operation. 2. Input specifications are measured from the 50% level of the rising edge of DLLIN to the 50% level of the signal. Timings are measured at the pin. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor Table 2-16. AC Timing for SIU Inputs ...
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... The maximum bus frequency depends on the mode: • In 60x-compatible mode connected to another MSC8103 device, the frequency is determined by adding the input and output longest timing values, which results in a frequency of 75 MHz for 30 pF output capacitance. In multi-master mode when connected to another MSC8103 device, the frequency is determined by adding the input and output longest timing values, which results in a frequency of 75 MHz for 30 pF output capacitance. • ...
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... Data bus inputs—ECC and parity modes Address bus/TT[0–4]/TC[0–2]/TBST/TSIZ[0–3]/GBL inputs Address bus/TT[0–4]/TC[0–2]/TBST/TSIZ[0–3]/GBL/BADDR[27–31] outputs AACK/ARTRY/ABB/TS/DBG/BG/BR/DBB/CS signals MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor DLLIN AACK/ARTRY/TA/TEA/DBG/BG/BR PSDVAL/ABB/DBB/TS inputs Data bus inputs— ...
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... HACK write minimum deassertion width after ICR, CVR and Data Register 5 writes 47 Host data input minimum set-up time before write data strobe deassertion Host data input minimum set-up time before HACK write deassertion MSC8103 Network Digital Signal Processor, Rev. 12 2-18 Table 2-18. DMA Signals Characteristic . ...
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... HRRQ/HRRQ is deasserted only when HOTX fifo is empty, HTRQ/HTRQ is deasserted only if HORX fifo is full (treat as level Host Request). 11. Compute the value using the expression. Figure 2-12 and Figure 2-13 show HDI16 read signal timing. Figure 2-14 and Figure 2-15 show HDI16 write signal timing. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor Host Interface (HDI16) Timing 3 Characteristics ...
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... HA[0–3] HCS[1–2] HD[0–15] HREQ (single host request) HRRQ (double host request) Figure 2-12. HA[0–3] HCS[1–2] HRD HD[0–15] HREQ (single host request) HRRQ (double host request) Figure 2-13. MSC8103 Network Digital Signal Processor, Rev HRW 44a HDS Read Timing Diagram, Single Data Strobe ...
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... HREQ (single host request) HTRQ (double host request) Figure 2-14. HA[0–3] HCS[1–2] HWR HD[0–15] HREQ (single host request) HTRQ (double host request) Figure 2-15. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor Write Timing Diagram, Single Data Strobe 57 58 ...
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... Physical and Electrical Specifications Figure 2-16 shows Host DMA read timing. Figure 2-16. Figure 2-17 shows Host DMA write timing. (Output) HD[0–15] (Output) Figure 2-17. MSC8103 Network Digital Signal Processor, Rev. 12 2-22 HREQ (Output) 64 44a HACK RX[0–3] Read 50 49 Data HD[0–15] Valid (Output) Host DMA Read Timing Diagram, HPCR[OAD ...
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... TDM output delay after low-to-high serial clock transition 42 PIO/TIMER/DMA output delay after low-to-high serial clock transition 2 Note: FCC, SCC, SMC, SPI are Non-Multiplexed Serial Interface signals. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor Table 2-20. CPM Input Characteristics Characteristic Table 2-21. CPM Output Characteristics ...
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... FCC inputs FCC outputs SCC/SMC/SPI/I2C inputs SCC/SMC/SPI/I2C outputs Figure 2-20. SCC/SMC/SPI/I2C inputs SCC/SMCSPI/I2C outputs Figure 2-21. Serial input clock TDM inputs TDM outputs MSC8103 Network Digital Signal Processor, Rev. 12 2-24 39b Figure 2-19. FCC External Clock Diagram BRGxO 18a 2 SCC/SMC/SPI/I C Internal Clock Diagram Serial input clock ...
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... TCK low to TDO high impedance 512 TRST assert time 513 TRST set-up time to TCK low TCK (Input) 503 Figure 2-24. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor DLLIN 23 22 PIO, Timer, and DMA Signal Diagram Table 2-22. JTAG Timing Characteristics 501 ...
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... TDO (Output) TDO (Output) TDO (Output) Figure 2-25. TCK (Input) TRST (Input) 512 MSC8103 Network Digital Signal Processor, Rev. 12 2-26 508 Input Data Valid 510 Output Data Valid 511 510 Output Data Valid Test Access Port Timing Diagram 513 Figure 2-26. TRST Timing Diagram ...
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... Packaging This chapter provides information about the MSC8103 package, including diagrams of the package pinouts and tables showing how the signals discussed in Chapter 1 are allocated. The MSC8103 is available in a 332-pin lidded flip chip-plastic ball grid array (FC-PBGA). 3.1 FC-PBGA Package Description Figure 3-1 and Figure 3-2 show top and bottom views of the FC-PBGA package, including pinouts. Table 3-1 lists the MSC8103 signals alphabetically by signal name ...
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... Note: Signal names in this figure are the default signals after reset, except for signals C2, C19, D1, D2, D18, E1, F3, H13, H14, and W11 which show the second configuration signal name. Figure 3-1. MSC8103 Flip Chip Plastic Ball Grid Array (FC-PBGA), Top View 3-2 Top View ...
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... Note: Signal names in this figure are the default signals after reset, except for signals C2, C19, D1, D2, D18, E1, F3, H13, H14, and W11 which show the second configuration signal name. Figure 3-2. MSC8103 Flip Chip Plastic Ball Grid Array (FC-PBGA), Bottom Vie MSC8103 Network Digital Signal Processor, Rev. 12 ...
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... Packaging Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 12 3-4 MSC8103 Signal Listing By Name Signal Name Number A0 W15 A1 N14 A2 V15 A3 T14 A4 U15 A5 W16 A6 V16 A7 W17 A8 U16 A9 V17 A10 W18 A11 U17 A12 T16 A13 V18 A14 V19 A15 R16 A16 T17 A17 U18 ...
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... Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor MSC8103 Signal Listing By Name (Continued) Signal Name Number ALE ARTRY BADDR27 BADDR28 BADDR29 BADDR30 BADDR31 BCTL0 BCTL1 BG BNKSEL0 BNKSEL1 BNKSEL2 BR BRG1O BRG1O BRG2O BRG2O BRG3O BRG4O BRG5O BRG6O BRG7O BRG8O BTM0 BTM1 ...
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... Packaging Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 12 3-6 MSC8103 Signal Listing By Name (Continued) Signal Name Number CLK5 CLK6 CLK7 CLK8 CLK9 CLK10 CLKIN CLKOUT COL for FCC1 COL for FCC2 CRS for FCC1 CRS for FCC2 CS0 CS1 CS2 CS3 CS4 ...
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... Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor MSC8103 Signal Listing By Name (Continued) Signal Name Number D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 ...
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... Packaging Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 12 3-8 MSC8103 Signal Listing By Name (Continued) Signal Name Number D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 DACK1 DACK2 DACK3 ...
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... Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor MSC8103 Signal Listing By Name (Continued) Signal Name Number DP4 DP5 DP6 DP7 DRACK1/DONE1 DRACK2/DONE2 DREQ1 DREQ2 DREQ3 DREQ4 EE0 EE1 EE2 EE3 EE4 EE5 EED EXT_BG2 EXT_BG3 EXT_BR2 EXT_BR3 EXT_DBG2 EXT_DBG3 EXT1 ...
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... Packaging Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 12 3-10 MSC8103 Signal Listing By Name (Continued) Signal Name Number GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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... Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor MSC8103 Signal Listing By Name (Continued) Signal Name Number HA2 HA3 HACK/HACK HCS1/HCS1 HCS2/HCS2 HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 HDDS HDS/HDS HDSP ...
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... Packaging Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 12 3-12 MSC8103 Signal Listing By Name (Continued) Signal Name IRQ1 IRQ2 IRQ2 IRQ2 IRQ3 IRQ3 IRQ3 IRQ4 IRQ5 IRQ5 IRQ6 IRQ7 IRQ7 L1RSYNC for SI1 TDMA1 L1RSYNC for SI2 TDMB2 L1RSYNC for SI2 TDMC2 L1RSYNC for SI2 TDMD2 ...
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... Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor MSC8103 Signal Listing By Name (Continued) Signal Name L1TXD1 for SI1 TDMA1 Nibble L1TXD2 for SI1 TDMA1 Nibble L1TXD3 for SI1 TDMA1 Nibble LIST1 for SI1 LIST1 for SI2 LIST2 for SI1 LIST2 for SI2 ...
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... Packaging Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 12 3-14 MSC8103 Signal Listing By Name (Continued) Signal Name Number PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 ...
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... Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor MSC8103 Signal Listing By Name (Continued) Signal Name Number PBS6 PBS7 PC4 PC5 PC6 PC7 PC12 PC13 PC14 PC15 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 PD7 PD16 PD17 PD18 ...
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... Packaging Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 12 3-16 MSC8103 Signal Listing By Name (Continued) Signal Name Number PGTA POE PORESET PPBS PSDA10 PSDAMUX PSDCAS PSDDQM0 PSDDQM1 PSDDQM2 PSDDQM3 PSDDQM4 PSDDQM5 PSDDQM6 PSDDQM7 PSDRAS PSDVAL PSDWE PUPMWAIT PWE0 PWE1 PWE2 PWE3 PWE4 PWE5 ...
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... Table 3-1. RXADDR2/RXCLAV1 for FCC1 UTOPIA 8 MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor MSC8103 Signal Listing By Name (Continued) Signal Name RSTCONF RTS for FCC1 RTS for FCC2 RTS/TENA for SCC1 RTS/TENA for SCC2 RX_DV for FCC1 RX_DV for FCC2 RX_ER for FCC1 ...
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... Packaging Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 12 3-18 MSC8103 Signal Listing By Name (Continued) Signal Name RXD3 for FCC2 MII/HDLC nibble RXD4 for FCC1 UTOPIA 8 RXD5 for FCC1 UTOPIA 8 RXD6 for FCC1 UTOPIA 8 RXD7 for FCC1 UTOPIA 8 RXENB for FCC1 RXPRTY for FCC1 UTOPIA 8 ...
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... Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor MSC8103 Signal Listing By Name (Continued) Signal Name TGATE1 TGATE2 THERM1 THERM2 TIN1/TOUT2 TIN2 TIN3/TOUT4 TIN4 TMCLK TMS TOUT1 TOUT3 TRST TS TSIZ0 TSIZ1 TSIZ2 TSIZ3 TT0 TT1 TT2 TT3 TT4 TX_EN for FCC1 MII ...
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... Packaging Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 12 3-20 MSC8103 Signal Listing By Name (Continued) Signal Name TXCLAV0 for FCC1 UTOPIA 8 TXCLAV1 for FCC1 UTOPIA 8 TXCLAV2 for FCC1 UTOPIA 8 TXCLAV3 for FCC1 UTOPIA 8 TXD for FCC1 transparent/HDLC serial TXD for FCC2 transparent/HDLC serial ...
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... Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor MSC8103 Signal Listing By Name (Continued) Signal Name Number DDH V DDH V DDH V DDH V DDH V DDH V DDH V DDH V DDH V DDH V DDH V DDH V DDH V DDH V DDH ...
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... B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 MSC8103 Network Digital Signal Processor, Rev. 12 3-22 MSC8103 Signal Listing by Pin Designator Signal Name IRQ5 / DP5 / DREQ4 / EXT_DBG3 D11 D17 D22 D27 D32 / HD0 D37 / HD5 D42 / HD10 D46 / HD14 ...
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... D13 D14 D15 D16 D17 D18 D19 MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor MSC8103 Signal Listing by Pin Designator (Continued) Signal Name D15 D20 D25 D30 D35 / HD3 D40 / HD8 D44 / HD12 D49 / HA1 D53 / HRW / HRD ...
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... F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 MSC8103 Network Digital Signal Processor, Rev. 12 3-24 MSC8103 Signal Listing by Pin Designator (Continued) Signal Name DDH D13 V DDH DDH V DDH DDH D47 / HD15 V DDH D56 / HACK / HRRQ ...
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... H18 H19 PA30 / FCC1:UTOPIA8:TXCLAV / FCC1:UTOPIA8:TXCLAV0 / FCC1:MII:CRS / J13 J14 J15 MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor MSC8103 Signal Listing by Pin Designator (Continued) Signal Name GND D12 GND D23 GND D33 / HD1 GND PSDVAL GND V DDH V DDH TEA ...
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... L18 L19 MSC8103 Network Digital Signal Processor, Rev. 12 3-26 MSC8103 Signal Listing by Pin Designator (Continued) Signal Name V DDH PSDAMUX / PGPL5 PGTA / PUPMWAIT / PPBS / PGPL4 PWE3 / PSDDQM3 / PBS3 PA28 / FCC1:UTOPIA8:RXENB / FCC1:MII:TX_EN PD29 / FCC1:UTOPIA8:RXADDR3 / FCC1:UTOPIA8:RXCLAV2 / SCC1:RTS/TENA PC29 / SCC1:CTS / SCC1:CLSN / BRG3O / CLK3 / TIN2 ...
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... MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor MSC8103 Signal Listing by Pin Designator (Continued) Signal Name PA16 / FCC1:UTOPIA8:RXD6 / FCC1:MII and HDLC nibble:RXD1 A21 A26 GND CS0 CS5 CS7 CS4 PC25 / DMA:DACK2 / BRG7O / CLK7 / TIN4 PA25 / FCC1:UTOPIA8:TXD0 / SDMA:MSNUM0 ...
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... R14 R15 R16 R17 R18 R19 MSC8103 Network Digital Signal Processor, Rev. 12 3-28 MSC8103 Signal Listing by Pin Designator (Continued) Signal Name PC4 / FCC2:CD / SMC1:SMRXD / SI2:LIST4 GND GND GND GND GND V DD A23 A27 A29 PC22 / SI1:LIST1 / DREQ1 / CLK10 SPARE1 ...
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... U17 U18 U19 V1 V2 PD19 / FCC1:UTOPIA8:TXADDR4 / FCC1:UTOPIA:TXCLAV3 / SPI:SPISEL / MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor MSC8103 Signal Listing by Pin Designator (Continued) Signal Name CLKOUT PA12 / FCC1:UTOPIA8:RXD2 / SDMA:MSNUM3 PC7 / FCC1:UTOPIA8:TXADDR2 / FCC1:UTOPIA8:TXADDR2/TXCLAV1 / FCC1:CTS / SI1:LIST1 PA6 / TDMA1:L1RSYNC AACK DDH A12 ...
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... W10 W11 W12 W13 W14 W15 W16 W17 W18 MSC8103 Network Digital Signal Processor, Rev. 12 3-30 MSC8103 Signal Listing by Pin Designator (Continued) Signal Name GND SYN PA11 / FCC1:UTOPIA8:RXD1 / SDMA:MSNUM4 PA7 / SMC2:SMSYN / TDMA1:L1TSYNC ABB / IRQ2 BG TSIZ0 TT3 A13 A14 PA18 / FCC1:UTOPIA8:TXD7 / FCC1:MII and HDLC nibble:TXD0 / ...
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... Lidded FC-PBGA Package Mechanical Drawing . Figure 3-3. Case 1473-01 Mechanical Information, 332-pin Lidded FC-PBGA Package MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor Lidded FC-PBGA Package Mechanical Drawing CASE 1473-01 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M–1994. 2. Dimensions in millimeters. 3. Maximum solder ball diameter measured parallel to Datum A ...
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... Packaging MSC8103 Network Digital Signal Processor, Rev. 12 3-32 Freescale Semiconductor ...
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... Design Considerations This chapter includes design and layout guidelines for manufacturing boards using the MSC8103. 4.1 Thermal Design Considerations The average chip-junction temperature where = ambient temperature ° θ = package thermal resistance INT I/O × W—chip internal power ...
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... External data memory writes occurs once every eight cycles with 50% of data pins switching. • Each address and data pin has total load at the pin. • The application operates at V DDH MSC8103 Network Digital Signal Processor, Rev sourced from the DD CCSYN ) of 0 ...
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... A four-layer board is recommended, employing two inner layers as All output pins on the MSC8103 have fast rise and fall times. Printed circuit board (PCB) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times ...
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... The V V CCSYN CCSYN1 user should also bypass and GND SYN possible to the chip package V DD Figure 4-2. MSC8103 Network Digital Signal Processor, Rev. 12 4-4 to and with a 0.01-µF capacitor as closely as GND V V SYN1 CCSYN CCSYN1 10Ω 10nH 10 µ ...
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...
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... Freescale™, the Freescale logo, and StarCore are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2001, 2008. Core Order Number (MHz) 275 MSC8103M1100F 275 MSC8103VT1100F 300 MSC8103M1200F 300 MSC8103VT1200F ...