MSC8103 Freescale Semiconductor / Motorola, MSC8103 Datasheet - Page 10

• Manufacturer Part Number: MSC8103
• Description: Network Digital Signal Processor
• Manufacturer: Freescale Semiconductor / Motorola

Signals/Connections
1.4 System Bus, HDI16, and Interrupt Signals
The system bus, HDI16, and interrupt signals are grouped together because they use a common set of signal lines.
Individual assignment of a signal to a specific signal line is configured through registers in the System Interface
Unit (SIU) and the Host Interface (HDI16). 1-5 describes the signals in this group.
Note: To boot from the host interface, the HDI16 must be enabled by pulling up the
1-6
BTM[0–1]
EE4
EE5
EED
PORESET
RSTCONF
HRESET
SRESET
Note:
Signal Name
1
1
1
PORESET
Internal Space Port Size bit in the Bus Control Register (BCR[ISPS]) to change the system data bus width
from 64 bits to 32 bits and reassign the upper 32 bits to their HDI16 functions. Never set the Host Port
Enable (HEN) bit in the Host Port Control Register (HPCR) to enable the HDI16, unless the bus size is
first changed from 64 bits to 32 bits. Otherwise, unpredictable operation may occur.
See the emulation and debug chapter in the SC140 DSP Core Reference Manual for details on how to configure these pins.
. The configuration word must then be loaded from the host. The configuration word must set the
Table 1-4.
Output
Output
Output
Type
Input
Input
Input
Input
Input
Input
Input
Input
MSC8103 Network Digital Signal Processor, Rev. 12
Reset, Configuration, and EOnCE Event Signals (Continued)
Boot Mode 0–1
Determines the MSC8103 boot mode when PORESET is deasserted. See the emulation and debug
chapter in the SC140 DSP Core Reference Manual for details on how to set these pins.
EOnCE Event 4
After PORESET is deasserted, you can configure EE4 as an input (default) or an output. See the
emulation and debug chapter in the SC140 DSP Core Reference Manual for details on the ETRSMT
Register.
Enable Address Event Detection Channel 4 or generate an EOnCE event.
The DSP wrote the EOnCE Transmit Register (ETRSMT). Triggers external debugging equipment.
EOnCE Event 5
After PORESET is deasserted, you can configure EE5 as an input (default) or an output.
Enable Address Event Detection Channel 5.
Detection by Address Event Detection Channel 5. Triggers external debugging equipment.
Enhanced OnCE (EOnCE) Event Detection
After PORESET is deasserted, you can configure EED as an input (default) or output:
Enable the Data Event Detection Channel.
Detection by the Data Event Detection Channel. Triggers external debugging equipment.
Power-On Reset
When asserted, this line causes the MSC8103 to enter power-on reset state.
Reset Configuration
Used during reset configuration sequence of the chip. A detailed explanation of its function is
provided in the “Power-On Reset Flow” and “Hardware Reset Configuration” sections of the
MSC8103 Reference Manual.
Hard Reset
When asserted, this open-drain line causes the MSC8103 to enter the hard reset state.
Soft Reset
When asserted, this open-drain line causes the MSC8103 to enter the soft reset state.
Signal Description
HPE
signal line during
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