MSC8103 Freescale Semiconductor / Motorola, MSC8103 Datasheet - Page 45

• Manufacturer Part Number: MSC8103
• Description: Network Digital Signal Processor
• Manufacturer: Freescale Semiconductor / Motorola

2.5.2.1 System Clock Control Register
SCCR is memory-mapped into the SIU register map of the MSC8103.
2.5.2.2 System Clock Mode Register
SCMR is a read-only register that is updated during power-on reset (PORESET) and provides the mode control
signals to the PLLs, DLL, and clock logic. This register reflects the currently defined configuration settings. For
details of the available setting options, see AN2306/D.
Freescale Semiconductor
Reset
Reset
Reset
Reset
Type
Type
Type
Type
Bit
Bit
CLKODIS
Bit
Bit
Bit No.
DFBRG
Name
28–29
30–31
0–26
27
—
—
16
16
0
0
PORESET
17
COREPDF
17
SPLLPDF
1
1
01
—
—
0
Defaults
18
18
2
2
Figure 2-2.
Figure 2-3.
Hard Reset
Unaffected
Unaffected
19
19
3
3
—
—
MSC8103 Network Digital Signal Processor, Rev. 12
20
20
4
4
System Clock Control Register (SCCR)—0x10C80
Table 2-7.
System Clock Mode Register (SCMR)—0x10C88
Reserved. Write to 0 fro future compatibility.
CLKOUT Disable
Disables the CLKOUT signal. The value of
CLKOUT when disabled is indeterminate (can be 1
or 0).
Reserved. Write to 0 fro future compatibility.
Division Factor for the BRG Clock Defines the
BRGCLK frequency. Changing this value does not
result in a loss of lock condition.
Reserved
21
21
—
—
5
5
COREMF
SPLLMF
22
22
6
6
SCCR Bit Descriptions
Description
23
23
7
Reserved
7
—
—
—
—
R
R
24
24
—
8
8
DLLDIS
25
25
9
9
BUSDF
10
26
10
26
—
CLKODIS
0
1
00
01
10
11
R/W
11
27
11
27
0
CLKOUT enabled (default)
CLKOUT disabled
Divide by 4
Divide by 16 (default value)
Divide by 64
Divide by 256
12
28
12
28
Reserved
—
—
Settings
Clock Configuration
13
29
13
29
COREDF
CPMDF
14
30
14
30
0
DFBRG
R/W
15
31
15
31
1
2-5