PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 98

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC17C7XX
12.1
When the T0CS (T0STA<5>) bit is set, TMR0 incre-
ments on the internal clock. When T0CS is clear, TMR0
increments on the external clock (RA1/T0CKI pin). The
external clock edge can be selected in software. When
the T0SE (T0STA<6>) bit is set, the timer will increment
on the rising edge of the RA1/T0CKI pin. When T0SE
is clear, the timer will increment on the falling edge of
the RA1/T0CKI pin. The prescaler can be programmed
to introduce a prescale of 1:1 to 1:256. The timer incre-
ments from 0000h to FFFFh and rolls over to 0000h.
On overflow, the TMR0 Interrupt Flag bit (T0IF) is set.
The TMR0 interrupt can be masked by clearing the cor-
responding TMR0 Interrupt Enable bit (T0IE). The
TMR0 Interrupt Flag bit (T0IF) is automatically cleared
when vectoring to the TMR0 interrupt vector.
FIGURE 12-1:
FIGURE 12-2:
DS30289B-page 98
RA1/T0CKI
Timer0 Operation
(T0STA<6>)
T0SE
Increment
Prescaler
Prescaler
(PSOUT)
Note 1: The delay from the T0CKI edge to the TMR0 increment is 3Tosc to 7Tosc.
Sampled
Output
Output
TMR0
TMR0
TIMER0 MODULE BLOCK DIAGRAM
TMR0 TIMING WITH EXTERNAL CLOCK (INCREMENT ON FALLING EDGE)
2:
3: The PSOUT high time is too short and is missed by the sampling circuit.
F
OSC
= PSOUT is sampled here.
(T0STA<5>)
/4
T0CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
0
1
(Note 1)
T0PS3:T0PS0
(T0STA<4:1>)
Prescaler
(8 Stage
Async Ripple
Counter)
T0
4
PSOUT
12.2
When an external clock input is used for Timer0, it is
synchronized with the internal phase clocks. Figure 12-
2 shows the synchronization of the external clock. This
synchronization is done after the prescaler. The output
of the prescaler (PSOUT) is sampled twice in every
instruction cycle to detect a rising or a falling edge. The
timing requirements for the external clock are detailed
in the electrical specification section.
12.2.1
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time TMR0 is actually
incremented. Figure 12-2 shows that this delay is
between 3T
suring the interval between two edges (e.g. period) will
be accurate within 4T
Synchronization
Q2
T0 + 1
Using Timer0 with External Clock
DELAY FROM EXTERNAL CLOCK
EDGE
OSC
Q4
and 7T
TMR0H<8> TMR0L<8>
OSC
OSC
(Note 3)
2000 Microchip Technology Inc.
( 121 ns @ 33 MHz).
T0 + 2
. Thus, for example, mea-
(Note 2)
Interrupt-on-Overflow
(INTSTA<5>)
sets T0IF