PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 82

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC17C7XX
10.5
PORTE is a 4-bit bi-directional port. The corresponding
data direction register is DDRE. A ’1’ in DDRE config-
ures the corresponding port pin as an input. A ’0’ in the
DDRE register configures the corresponding port pin
as an output. Reading PORTE reads the status of the
pins, whereas writing to PORTE will write to the port
latch. PORTE is multiplexed with the system bus.
When operating as the system bus, PORTE contains
the
(AD15:AD0). These control signals are Address Latch
Enable (ALE), Output Enable (OE) and Write (WR).
The control signals OE and WR are active low signals.
The timing for the system bus is shown in the Electrical
Specifications section.
FIGURE 10-11:
DS30289B-page 82
Note: I/O pins have protection diodes to V
Note:
control
PORTE and DDRE Register
Three pins of this port are configured as
the system bus when the device’s configu-
ration bits are selected to Microprocessor
or Extended Microcontroller modes. The
other pin is a general purpose I/O or
Capture4 pin. In the two other micro-
controller modes, RE2:RE0 are general
purpose I/O pins.
signals
BLOCK DIAGRAM OF RE2:RE0 (IN I/O PORT MODE)
for
TTL
Input
Buffer
the
0
1
address/data
Data
Port
DD
and V
R
Q
Q
SS
.
CK
CK
S
bus
D
D
Example 10-5 shows an instruction sequence to initial-
ize PORTE. The Bank Select Register (BSR) must be
selected to Bank 1 for the port to be initialized. The fol-
lowing example uses the MOVLB instruction to load the
BSR register for bank selection.
EXAMPLE 10-5:
MOVLB
CLRF
MOVLW
MOVWF
1
PORTE, F
0x03
DDRE
; Select Bank 1
; Initialize PORTE data
; latches before setting
; the data direction
; register
; Value used to initialize
; data direction
; Set RE<1:0> as inputs
; RE<3:2> as outputs
; RE<7:4> are always
; read as ’0’
INITIALIZING PORTE
WR_PORTE
RD_PORTE
2000 Microchip Technology Inc.
WR_DDRE
RD_DDRE
DRV_SYS
Data Bus
EX_EN
CNTL
System Bus
Control