PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 104

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC17C7XX
13.1
13.1.1
Both Timer1 and Timer2 will operate in 8-bit mode
when the T16 bit is clear. These two timers can be inde-
pendently configured to increment from the internal
instruction cycle clock (T
source on the RB4/TCLK12 pin. The timer clock source
is configured by the TMRxCS bit (x = 1 for Timer1,
or = 2 for Timer2). When TMRxCS is clear, the clock
source is internal and increments once every instruc-
tion cycle (F
source is the RB4/TCLK12 pin and the counters will
increment on every falling edge of the RB4/TCLK12
pin.
The timer increments from 00h until it equals the Period
register (PRx). It then resets to 00h at the next incre-
ment cycle. The timer interrupt flag is set when the
timer is reset. TMR1 and TMR2 have individual inter-
rupt flag bits. The TMR1 interrupt flag bit is latched into
TMR1IF and the TMR2 interrupt flag bit is latched into
TMR2IF.
FIGURE 13-1:
DS30289B-page 104
RB4/TCLK12
Timer1 and Timer2
TIMER1, TIMER2 IN 8-BIT MODE
OSC
/4). When TMRxCS is set, the clock
F
F
OSC
OSC
TIMER1 AND TIMER2 IN TWO 8-BIT TIMER/COUNTER MODE
/4
/4
CY
), or from an external clock
TMR1CS
(TCON1<0>)
TMR2CS
(TCON1<1>)
0
1
1
0
(TCON2<0>)
TMR1ON
(TCON2<1>)
TMR2ON
Comparator<8>
Comparator<8>
Comparator x8
Comparator x8
TMR1
TMR2
Each timer also has a corresponding interrupt enable
bit (TMRxIE). The timer interrupt can be enabled/
disabled by setting/clearing this bit. For peripheral
interrupts to be enabled, the Peripheral Interrupt
Enable bit must be set (PEIE = ’1’) and global interrupt
must be enabled (GLINTD = ’0’).
The timers can be turned on and off under software
control. When the timer on control bit (TMRxON) is set,
the timer increments from the clock source. When
TMRxON is cleared, the timer is turned off and cannot
cause the timer interrupt flag to be set.
13.1.1.1
When TMRxCS is set, the clock source is the RB4/
TCLK12 pin, and the counter will increment on every
falling edge on the RB4/TCLK12 pin. The TCLK12
input is synchronized with internal phase clocks. This
causes a delay from the time a falling edge appears on
TCLK12 to the time TMR1 or TMR2 is actually incre-
mented. For the external clock input timing require-
ments, see the Electrical Specification section.
PR1
PR2
External Clock Input for Timer1 and
Timer2
Equal
Equal
RESET
RESET
Set TMR1IF
(PIR1<4>)
Set TMR2IF
(PIR1<5>)
2000 Microchip Technology Inc.