PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 24

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC17C7XX
5.1
5.1.1
The Power-on Reset circuit holds the device in RESET
until V
2.3V). The devices produce an internal RESET for both
rising and falling V
just tie the MCLR/V
to V
usually needed to create Power-on Reset. A minimum
rise time for V
tions for details.
Figure 5-2 and Figure 5-3 show two possible POR
circuits.
FIGURE 5-2:
FIGURE 5-3:
DS30289B-page 24
Note 1: An external Power-on Reset circuit is
DD
DD
. This will eliminate external RC components
V
2: R < 40 k is recommended to ensure that the
3: R1 = 100
DD
Power-on Reset (POR), Power-up
Timer (PWRT), Oscillator Start-up
Timer (OST) and Brown-out Reset
(BOR)
is above the trip point (in the range of 1.4V -
D
POWER-ON RESET (POR)
required only if V
slow. The diode D helps discharge the capac-
itor quickly when V
voltage drop across R does not exceed 0.2V
(max. leakage current spec. on the MCLR/
V
degrade V
ing into MCLR from external capacitor C in
the event of MCLR/V
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
PP
DD
V
pin is 5 A). A larger voltage drop will
DD
V
is required. See Electrical Specifica-
R
DD
DD
PP
C
. To take advantage of the POR,
IH
pin directly (or through a resistor)
USING ON-CHIP POR
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
to 1 k will limit any current flow-
level on the MCLR/V
PIC17CXXX
V
MCLR
R1
DD
DD
DD
power-up time is too
PP
powers down.
DD
PIC17CXXX
pin breakdown due to
MCLR
POWER-UP)
PP
pin.
5.1.2
The Power-up Timer provides a fixed 96 ms time-out
(nominal) on power-up. This occurs from the rising
edge of the internal POR signal if V
tied, or after the first rising edge of MCLR (detected
high). The Power-up Timer operates on an internal RC
oscillator. The chip is kept in RESET as long as the
PWRT is active. In most cases, the PWRT delay allows
V
The power-up time delay will vary from chip to chip and
with V
details.
5.1.3
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (1024T
is invoked, or a wake-up from SLEEP event occurs in XT
or LF mode. The PWRT and OST operate in parallel.
The OST counts the oscillator pulses on the OSC1/
CLKIN pin. The counter only starts incrementing after
the amplitude of the signal reaches the oscillator input
thresholds. This delay allows the crystal oscillator or
resonator to stabilize before the device exits RESET.
The length of the time-out is a function of the crystal/
resonator frequency.
Figure 5-4 shows the operation of the OST circuit. In
this figure, the oscillator is of such a low frequency that
although enabled simultaneously, the OST does not
time-out until after the Power-up Timer time-out.
FIGURE 5-4:
DD
This figure shows in greater detail the timings involved
with the oscillator start-up timer. In this example, the low
frequency crystal start-up time is larger than power-up
time (T
T
lation level detectable by the Oscillator Start-up Timer
(OST).
T
INTERNAL RESET
OSC
OST
PWRT TIME_OUT
to rise to an acceptable level.
OST TIME_OUT
DD
1 = time for the crystal oscillator to react to an oscil-
= 1024T
PWRT
and temperature. See DC parameters for
POWER-UP TIMER (PWRT)
OSCILLATOR START-UP TIMER
(OST)
OSC2
MCLR
).
V
OSC
DD
.
POR or BOR Trip Point
T
OSC
OSC
OSCILLATOR START-UP
TIME (LOW FREQUENCY)
1
) delay whenever the PWRT
2000 Microchip Technology Inc.
T
PWRT
T
DD
OST
and MCLR are