PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 169

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

15.2.15
Clock arbitration occurs when the master, during any
receive, transmit, or Repeated Start/Stop condition, de-
asserts the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the baud rate gen-
erator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is sam-
pled high, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and begins counting. This
ensures that the SCL high time will always be at least
one BRG rollover count, in the event that the clock is
held low by an external device (Figure 15-33).
FIGURE 15-33:
BRG Overflow,
Release SCL,
If SCL = 1 Load BRG with
SSPADD<6:0>, and Start Count
to measure high time interval.
2000 Microchip Technology Inc.
SCL
SDA
CLOCK ARBITRATION
CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
T
BRG
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
T
BRG
SCL line sampled once every machine cycle (T
Hold off BRG until SCL is sampled high.
15.2.16
While in SLEEP mode, the I
addresses or data and when an address match or com-
plete byte transfer occurs, wake the processor from
SLEEP (if the SSP interrupt is enabled).
15.2.17
A RESET disables the SSP module and terminates the
current transfer.
SLEEP OPERATION
EFFECTS OF A RESET
T
BRG
SCL = 1 BRG starts counting
clock high interval.
PIC17C7XX
2
C module can receive
OSC
DS30289B-page 169
4).