PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 136

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC17C7XX
REGISTER 15-3: SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS 12h, BANK 6)
DS30289B-page 136
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
GCEN: General Call Enable bit (in I
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit (in I
In Master Transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
ACKDT: Acknowledge Data bit (in I
In Master Receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a
receive.
1 = Not Acknowledge
0 = Acknowledge
ACKEN: Acknowledge Sequence Enable bit (in I
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit AKDT data bit.
0 = Acknowledge sequence idle
RCEN: Receive Enable bit (in I
1 = Enables Receive mode for I
0 = Receive idle
PEN: STOP Condition Enable bit (in I
SCK Release Control:
1 = Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.
0 = STOP condition idle
RSEN: Repeated Start Condition Enabled bit (in I
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition idle
SEN: START Condition Enabled bit (In I
1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.
0 = START condition idle.
Legend:
R = Readable bit
- n = Value at POR Reset
R/W-0
GCEN
Note:
Note:
Note:
Note:
Note:
Automatically cleared by hardware.
If the I
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
If the I
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
If the I
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
If the I
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
If the I
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
ACKSTAT
R/W-0
2
2
2
2
2
C module is not in the IDLE mode, this bit may not be set (no spooling) and
C module is not in the IDLE mode, this bit may not be set (no spooling) and
C module is not in the IDLE mode, this bit may not be set (no spooling) and
C module is not in the IDLE mode, this bit may not be set (no spooling) and
C module is not in the IDLE mode, this bit may not be set (no spooling) and
ACKDT
R/W-0
W = Writable bit
’1’ = Bit is set
2
2
C Master mode only)
C
2
2
C Master mode only)
C Slave mode only)
2
ACKEN
C Master mode only)
R/W-0
2
2
C Master mode only)
C Master mode only)
2
2
C Master mode only)
C Master mode only)
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
R/W-0
RCEN
R/W-0
PEN
2000 Microchip Technology Inc.
x = Bit is unknown
R/W-0
RSEN
R/W-0
SEN
bit 0