PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 125

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

14.2.2
The receiver block diagram is shown in Figure 14-2.
The data comes in the RX/DT pin and drives the data
recovery block. The data recovery block is actually a
high speed shifter operating at 16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at F
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the receive (serial) shift reg-
ister (RSR). After sampling the STOP bit, the received
data in the RSR is transferred to the RCREG (if it is
empty). If the transfer is complete, the interrupt bit,
RCIF, is set. The actual interrupt can be enabled/
disabled by setting/clearing the RCIE bit. RCIF is a
read only bit which is cleared by the hardware. It is
cleared when RCREG has been read and is empty.
RCREG is a double buffered register (i.e., it is a two-
deep FIFO). It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third byte begin shifting to the RSR. On detection of the
STOP bit of the third byte, if the RCREG is still full, then
the overrun error bit, OERR (RCSTA<1>) will be set.
The word in the RSR will be lost. RCREG can be read
twice to retrieve the two bytes in the FIFO. The OERR
bit has to be cleared in software which is done by reset-
FIGURE 14-5:
FIGURE 14-6:
2000 Microchip Technology Inc.
(RX/DT pin)
Baud CLK
x16 CLK
USART ASYNCHRONOUS
RECEIVER
OSC
RX
.
Q2, Q4 CLK
RX PIN SAMPLING SCHEME
START BIT DETECT
(RX/DT pin)
x16 CLK
1
RX
2
3
RX sampled low
4
5
6
First rising edge of x16 clock after RX pin goes low
7
Samples
8
START bit
ting the receive logic (CREN is set). If the OERR bit is
set, transfers from the RSR to RCREG are inhibited, so
it is essential to clear the OERR bit if it is set. The fram-
ing error bit FERR (RCSTA<2>) is set if a STOP bit is
not detected.
14.2.3
The data on the RX/DT pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RX/DT pin. The sampling is done
on the seventh, eighth and ninth falling edges of a x16
clock (Figure 14-5).
The x16 clock is a free running clock and the three
sample points occur at a frequency of every 16 falling
edges.
9
Note:
10
Baud CLK for all but START bit
11
The FERR and the 9th receive bit are buff-
ered the same way as the receive data.
Reading the RCREG register will allow the
RX9D and FERR bits to be loaded with val-
ues for the next received data. Therefore,
it is essential for the user to read the
RCSTA register before reading RCREG, in
order not to lose the old FERR and RX9D
information.
SAMPLING
START bit
12
13
14
PIC17C7XX
15
16
DS30289B-page 125
1
Bit0
2
3