PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 34

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC17C7XX
6.1
The Interrupt Status/Control register (INTSTA) contains
the flag and enable bits for non-peripheral interrupts.
The PEIF bit is a read only, bit wise OR of all the periph-
eral flag bits in the PIR registers (Figure 6-4 and
Figure 6-5).
REGISTER 6-1: INTSTA REGISTER (ADDRESS: 07h, UNBANKED)
DS30289B-page 34
Note:
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Interrupt Status Register (INTSTA)
All interrupt flag bits get set by their speci-
fied condition, even if the corresponding
interrupt enable bit is clear (interrupt dis-
abled), or the GLINTD bit is set (all inter-
rupts disabled).
Legend:
R = Readable bit
- n = Value at POR Reset
bit 7
PEIF: Peripheral Interrupt Flag bit
This bit is the OR of all peripheral interrupt flag bits AND’ed with their corresponding enable bits.
The interrupt logic forces program execution to address (20h) when a peripheral interrupt is
pending.
1 = A peripheral interrupt is pending
0 = No peripheral interrupt is pending
T0CKIF: External Interrupt on T0CKI Pin Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to address (18h).
1 = The software specified edge occurred on the RA1/T0CKI pin
0 = The software specified edge did not occur on the RA1/T0CKI pin
T0IF: TMR0 Overflow Interrupt Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to address (10h).
1 = TMR0 overflowed
0 = TMR0 did not overflow
INTF: External Interrupt on INT Pin Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to address (08h).
1 = The software specified edge occurred on the RA0/INT pin
0 = The software specified edge did not occur on the RA0/INT pin
PEIE: Peripheral Interrupt Enable bit
This bit acts as a global enable bit for the peripheral interrupts that have their corresponding
enable bits set.
1 = Enable peripheral interrupts
0 = Disable peripheral interrupts
T0CKIE: External Interrupt on T0CKI Pin Enable bit
1 = Enable software specified edge interrupt on the RA1/T0CKI pin
0 = Disable interrupt on the RA1/T0CKI pin
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enable TMR0 overflow interrupt
0 = Disable TMR0 overflow interrupt
INTE: External Interrupt on RA0/INT Pin Enable bit
1 = Enable software specified edge interrupt on the RA0/INT pin
0 = Disable software specified edge interrupt on the RA0/INT pin
PEIF
R-0
T0CKIF
R/W-0
R/W-0
T0IF
W = Writable bit
’1’ = Bit is set
R/W-0
INTF
Care should be taken when clearing any of the INTSTA
register enable bits when interrupts are enabled
(GLINTD is clear). If any of the INTSTA flag bits (T0IF,
INTF, T0CKIF, or PEIF) are set in the same instruction
cycle as the corresponding interrupt enable bit is cleared,
the device will vector to the RESET address (0x00).
Prior to disabling any of the INTSTA enable bits, the
GLINTD bit should be set (disabled).
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
PEIE
T0CKIE
R/W-0
2000 Microchip Technology Inc.
x = Bit is unknown
R/W-0
T0IE
R/W-0
INTE
bit 0