PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 107

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

13.1.3
Three high speed pulse width modulation (PWM) out-
puts are provided. The PWM1 output uses Timer1 as
its time base, while PWM2 and PWM3 may indepen-
dently be software configured to use either Timer1 or
Timer2 as the time base. The PWM outputs are on the
RB2/PWM1, RB3/PWM2 and RG5/PWM3 pins.
Each PWM output has a maximum resolution of 10-
bits. At 10-bit resolution, the PWM output frequency is
32.2 kHz (@ 32 MHz clock) and at 8-bit resolution the
PWM output frequency is 128.9 kHz. The duty cycle of
the output can vary from 0% to 100%.
Figure 13-3 shows a simplified block diagram of a
PWM module.
The duty cycle registers are double buffered for glitch
free operation. Figure 13-4 shows how a glitch could
occur if the duty cycle registers were not double
buffered.
FIGURE 13-4:
2000 Microchip Technology Inc.
Output
PWM
Note:
USING PULSE WIDTH
MODULATION (PWM) OUTPUTS
WITH TIMER1 AND TIMER2
The dotted line shows PWM output if duty cycle registers were not double buffered.
If the new duty cycle is written after the timer has passed that value, then the PWM does
not reset at all during the current cycle, causing a “glitch”.
In this example, PWM period = 50. Old duty cycle is 30. New duty cycle value is 10.
PWM OUTPUT (NOT BUFFERED)
Timer
Interrupt
0
10
Write New
PWM Duty Cycle Value
20
30
40
0
Timer Interrupt
New PWM Duty Cycle Value
Transferred to Slave
The user needs to set the PWM1ON bit (TCON2<4>)
to enable the PWM1 output. When the PWM1ON bit is
set, the RB2/PWM1 pin is configured as PWM1 output
and forced as an output, irrespective of the data direc-
tion bit (DDRB<2>). When the PWM1ON bit is clear,
the pin behaves as a port pin and its direction is con-
trolled by its data direction bit (DDRB<2>). Similarly,
the PWM2ON (TCON2<5>) bit controls the configura-
tion of the RB3/PWM2 pin and the PWM3ON
(TCON3<0>) bit controls the configuration of the RG5/
PWM3 pin.
FIGURE 13-3:
Note 1: 8-bit timer is concatenated with 2-bit internal
PWxDCH
(Slave)
10
Comparator
Duty Cycle Registers
PRy
TMRx
Q clock or 2 bits of the prescaler to create
10-bit time base.
Comparator
20
(Note 1)
30
SIMPLIFIED PWM BLOCK
DIAGRAM
Clear Timer,
PWMx pin and
Latch D.C.
PIC17C7XX
40
Write
Read
PWxDCL<7:6>
R
S
DS30289B-page 107
0
Q
PWMxON
PWMx