PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 143

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

15.2
The MSSP module in I
master and slave functions (including general call sup-
port) and provides interrupts on START and STOP bits
in hardware to determine a free bus (multi-master func-
tion). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit
addressing.
Refer to Application Note AN578, “Use of the SSP
Module in the I
A “glitch” filter is on the SCL and SDA pins when the pin
is an input. This filter operates in both the 100 kHz and
400 kHz modes. In the 100 kHz mode, when these pins
are an output, there is a slew rate control of the pin that
is independent of device frequency.
FIGURE 15-10:
 2000 Microchip Technology Inc.
SDA
SCL
MSSP I
2
Read
Clock
C Multi-Master Environment.”
Shift
2
C Operation
MSb
STOP bit Detect
I
DIAGRAM
2
Match Detect
SSPADD reg
SSPBUF reg
START and
SSPSR reg
2
C SLAVE MODE BLOCK
C mode fully implements all
LSb
Write
(SSPSTAT reg)
Data Bus
Internal
Set, Reset
S, P bits
Addr Match
FIGURE 15-11:
Two pins are used for data transfer. These are the SCL
pin, which is the clock and the SDA pin, which is the
data. The SDA and SCL pins are automatically config-
ured when the I
functions are enabled by setting SSP Enable bit
SSPEN (SSPCON1<5>).
The MSSP module has six registers for I
These are the:
• SSP Control Register1 (SSPCON1)
• SSP Control Register2 (SSPCON2)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly acces-
• SSP Address Register (SSPADD)
The SSPCON1 register allows control of the I
ation. Four mode selection bits (SSPCON1<3:0>) allow
one of the following I
• I
• I
• I
Before selecting any I
must be programmed to inputs by setting the appropri-
ate DDR bits. Selecting an I
SSPEN bit, enables the SCL and SDA pins to be used
as the clock and data lines in I
sible
SDA
SCL
Baud Rate Generator
2
2
2
SSPADD<6:0>
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Master mode, clock = OSC/4 (SSPADD +1)
7
Read
2
Clock
Shift
C mode is enabled. The SSP module
MSb
START and STOP bit
2
C modes to be selected:
2
I
BLOCK DIAGRAM
Detect/Generate
C mode, the SCL and SDA pins
2
Match Detect
SSPADD reg
SSPBUF reg
SSPSR reg
PIC17C7XX
C MASTER MODE
2
2
C mode, by setting the
C mode.
LSb
DS30289B-page 143
Write
(SSPSTAT reg)
Clear/Set P, bit
and Set SSPIF
Set/Clear S bit
Data Bus
2
Internal
C operation.
Addr Match
and
2
C oper-