Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 99

• Manufacturer Part Number: Z8038018FSG
• Description: IC 16 BIT Z80 MPU 100-QFP
• Manufacturer: Zilog

Specifications of Z8038018FSG

• Processor Type: Z380
• Features: 16-Bit, High-Performance Enhanced Z80 CPU
• Speed: 18MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z80380x
• Core: Z380
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 18 MHz
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7
UMCSR0: 00000002H
R/W
Upper Memory Chip Select Control
The upper boundary for this memory area is address
00FFFFFFH. A user can define the area immediately below
this boundary with a size that is an integer power of two,
starting at 4 Kbytes. That is, the upper memory area can be
either 4 Kbytes, 8 Kbytes, 16 Kbytes and so on. The /UMCS
signal can be enabled to go active during refresh transac-
tions.
Upper Memory Chip Select Register 0
MA15-MA12 (Match Address Bits 15-12). If a match ad-
dress bit is at logic 1, the corresponding address signal of
a memory transaction is compared for a logic 1, as a
condition for /UMCS to become active. If the match ad-
dress bit is at logic 0, the corresponding address signal is
not compared (don't care). For example, MA12 deter-
mines if A12 should be tested for a logic 1 in memory
transactions.
Reserved bits 3-1. Read as 0s, should write to as 0s.
ERF (Enable for Refresh Transactions). If this bit is pro-
grammed to a logic 1, /UMCS goes active during
refresh transactions.
MA15 MA14 MA13
0
Figure 34. Upper Memory Chip Select Register 0
0
0
MA12
0
- -
0
- -
0
- -
0
ERF
0
0
<- Reset Value
Match Address Bits 15-12
Enable for Refresh
Reserved
Program as 0
Read as 0
Upper Memory Chip Select Register 1
MA23-MA16 (Match Address Bits 23-16). If a match ad-
dress bit is at logic 1, the corresponding address signal of
a memory transaction is compared for a logic 1, as a
condition for /UMCS to become active. If the mask address
bit is at logic 0, the corresponding address signal is not
compared (don't care). For example, MA23 determines if
A23 should be tested for a logic 1 in memory transactions.
Note that in order for/UMCS to go active in a memory
transaction, the /UMCS function has to be enabled in the
Memory Selects Master Enable Register (described later),
all the address signals A31-A24 at logic 0s, and all the
address signals A23-A12 programmed for address match-
ing in the above registers have to be at logic 1s. To define
the upper memory area as 4 Kbytes, MA23-MA12 should
be programmed with 1s. For an area larger than 4 Kbytes,
MA23-MA12 (in that order) should be programmed with
contiguous 1s followed by contiguous 0s. This is the
intended usage to maintain the upper memory area as a
single block. Note also that /UMCS can be enabled for
refresh transactions independent of the value programmed
into the Memory Selects Master Enable Register.
UMCSR1: 00000003H
R/W
7
MA23
Figure 35. Upper Memory Chip Select Register 1
1
MA22 MA21 MA20 MA19 MA18 MA17 MA16
1
1
1
0
0
0
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0
0
<- Reset Value
Match Address
Bits 23-16