Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 98

• Manufacturer Part Number: Z8038018FSG
• Description: IC 16 BIT Z80 MPU 100-QFP
• Manufacturer: Zilog

Specifications of Z8038018FSG

• Processor Type: Z380
• Features: 16-Bit, High-Performance Enhanced Z80 CPU
• Speed: 18MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z80380x
• Core: Z380
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 18 MHz
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lower Memory Chip Select Control
This memory area has its lower boundary at address
000000000H. A user can define the size to be an integer
power of two, starting at 4 Kbytes. For example, the lower
memory area can be either 4 Kbytes, 8 Kbytes, 16 Kbytes,
etc., starting from address 0. The /LMCS signal can be
enabled to go active during refresh transactions.
Lower Memory Chip Select Register 0
MA15-MA12 (Match Address Bits 15-12). If a match ad-
dress bit is at logic 1, the corresponding address signal of
a memory transaction is compared for a logic 0, as a
condition for /LMCS to become active. If the match ad-
dress bit is at logic 0, the corresponding address signal is
not compared (don't care). For example, MA12 deter-
mines if A12 should be tested for a logic 0 in memory
transactions.
Reserved bits 3-1. Read as 0s, should write to as 0s.
ERF (Enable for Refresh transactions). If this bit is pro-
grammed to a logic one, /LMCS goes active during refresh
transactions.
7
LMCSR0: 00000000H
R/W
MA15
Figure 32. Lower Memory Chip Select Register 0
0
MA14 MA13 MA12
0
0
0
- -
0
- -
0
- -
0
ERF
0
0
<- Reset Value
Enable for Refresh
Reserved
Program as 0
Read as 0
Match Address Bits 15-12
Lower Memory Chip Select Register 1
MA23-MA16 (Match Address Bits 23-16). If a
match address bit is at logic 1, the corresponding address
signal of a memory transaction is compared for a logic 0,
as a condition for /LMCS to become active. If the match
address bit is at logic 0, the corresponding address signal
is not compared (don't care). For example, MA23 deter-
mines if A23 should be tested for a logic 0 in memory
transactions. Note that in order for /LMCS to go active in a
memory transaction, the /LMCS function has to be enabled
in the Memory Selects Master Enable Register (described
later), all the address signals A31-A24 at logic 0s, and all
the address signals A23-A12 programmed for address
matching in the above registers have to be at logic 0s. To
define the lower memory area as 4 Kbytes, MA23-MA12
should be programmed with 1s. For an area larger than 4
Kbytes, MA23-MA12 (in that order) should be programmed
with contiguous 1s followed by contiguous 0s. This is the
intended usage to maintain the lower memory area as a
single block. Note also that /LMCS can be enabled for
refresh transactions independent of the value programmed
into the Memory Selects Master Enable Register.
7
LMCSR1: 00000001H
R/W
MA23 MA22 MA21
Figure 33. Lower Memory Chip Select Register 1
1
1
1
MA20 MA19 MA18 MA17 MA16
1
0
0
0
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0
0
<- Reset Value
Match Address
Bits 23-16