Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 9

• Manufacturer Part Number: Z8038018FSG
• Description: IC 16 BIT Z80 MPU 100-QFP
• Manufacturer: Zilog

Specifications of Z8038018FSG

• Processor Type: Z380
• Features: 16-Bit, High-Performance Enhanced Z80 CPU
• Speed: 18MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z80380x
• Core: Z380
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 18 MHz
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PS010002-0708
/EV
mal operation. When it is driven to logic 0, the Z380 MPU conditions itself in the reset
mode and tri-states all of its output pin drivers.
/HALT
is not selected, a Sleep instruction is executed no different than a Halt instruction, and the
one HALT signal goes active to indicate the CPU's HALT state. If the standby mode
option is selected, this signal goes active only at the Halt instruction execution.
/STNBY
selected, executing a sleep instruction stops clocking within the Z380 MPU and at BUS-
CLK and IOCLK after which this signal is asserted. The Z380 MPU is then in the low
power standby mode, with all operations suspended.
/INT3-0
maskable interrupt inputs.
IOCLK
divided-down version of BUSCLK. The division factor can be two, four, six or eight with
I/O transactions and interrupt-acknowledge transactions occurring relative to IOCLK.
/INTAK
distinguish between I/O and interrupt acknowledge transactions. This signal is High dur-
ing I/O read and I/O write transactions and Low during interrupt acknowledge transac-
tions.
/IORQ
I/O read and write transactions and interrupt acknowledge transactions.
/M1
rupt acknowledge and RETI transactions.
/IORD
data from the peripherals during I/O read transactions. In addition, /IORD is active during
the special RETI transaction and the I/O heartbeat cycle in the Z80 protocol case.
/IOWR
strobe data into the peripherals during I/O write transactions.
/LMCS
during a memory read or memory write transaction when accessing the lower portion of
the linear address space within the first 16 Mbytes, but only if this chip select function is
enabled.
/MCS3-/MCS0
nals are individually active during memory read or write transactions when accessing the
mid-range portions of the linear address space within the first 16 Mbytes. These signals
can be individually enabled or disabled.
/MRD
addressed memory location should place its data on the data bus as specified by the /
Evaluation Mode (input, active Low). This input should be left unconnected for nor-
Machine Cycle One (output, active Low, tri-state). This signal is active during inter-
Memory Read (output, active Low, tri-state). This signal indicates that the
Input, Output Read Strobe (output, active Low, tri-state). This signal is used strobe
Input/Output Write Strobe (output, active Low, tri-state). This signal is used to
I/O Clock (output, active High, tri-state). This signal is a program controlled
Input/Output Request (output, active Low, tri-state). This signal is active during all
Low Memory Chip Select (output, active Low, tri-state). This signal is activated
Halt Status (output, active Low, tri-state). If the Z380 MPU standby mode option
Interrupt Requests (inputs, active Low). These signals are four asynchronous
Interrupt Acknowledge Status (output, active Low, tri-state). This signal is used to
Standby Status (output, active Low, tri-state). If the Z380 MPU standby mode is
Mid-range Memory Chip Selects (output, active Low, tri-state). These sig-
Z380 Microprocessor
Product Specification
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