Z8038018FSG Zilog, Z8038018FSG Datasheet

Page 1

Thank you for your interest in the Z380 associated family of products. This Technical Manual describes programming and operation of the Z380 Z380 Microprocessor Unit (MPU), and products built around Z380 This Z380 User's Manual consists of the following Sections: ...

Page 2

... THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MER- CHANTABILITY OR FITNESS FOR ANY PURPOSE. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. ...

Page 3

Z ILOG 1.1 INTRODUCTION The Z380 CPU incorporates advanced architectural fea- tures that allow fast and efficient throughput and increased memory addressing capabilities while maintaining Z80 CPU and Z180 ® MPU object-code compatibility. The Z380 CPU core provides a continuing ...

Page 4

Z ILOG 1.1 INTRODUCTION (Continued) BCz DEz HLz IXz IYz BCz' DEz' HLz' IXz' IYz' Iz SPz PCz 1 IXU IYU IXU' IYU ™ Figure 1-1. Z380 CPU Register Architecture ...

Page 5

Z ILOG 1.2 CPU ARCHITECTURE The Z380 CPU is a binary-compatible extension of the Z80 CPU and the Z180 CPU architecture. High throughput rates are achieved by a high clock rate, high bus band- width, and instruction fetch/execute overlap. Communi- ...

Page 6

Z ILOG 1.2.2 Address Spaces (Continued) Each register set includes the primary registers IX, and IY, as well as the alternate registers A’, F’, B’, C’, D’, E’, H’, L’, IX’, and ...

Page 7

Z ILOG are handled by a newly added interrupt handing mode, “Assigned Vectored Mode,” which is a fixed vectored interrupt mode similar in interrupt handling to the Z180’s interrupts from on-chip peripherals. For handling interrupt requests on the /INT0 line, ...

Page 8

... THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MER- CHANTABILITY OR FITNESS FOR ANY PURPOSE. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. ...

Page 9

Z ILOG 2.1 INTRODUCTION The Z380 CPU supports five address spaces correspond- ing to the different types of locations that can be ad- dressed and the method by which the logical addresses are formed. These five address spaces are: CPU ...

Page 10

Z ILOG 2.2 CPU REGISTER SPACE (Continued) BCz DEz HLz IXz IYz BCz' DEz' HLz' IXz' IYz' Iz SPz PCz Figure 2-1. Register File Organization (Z380 MPU) 2-2 4 Sets of Registers ...

Page 11

Z ILOG 2.2.1 Primary and Working Registers The working register set is divided into two register files: the primary file and the alternate file (designated by prime (‘)). Each file contains an 8-bit accumulator (A), a Flag register (F), and ...

Page 12

Z ILOG 2.2.6 Stack Pointer (Continued) Increment/decrement of the Stack Pointer is affected by modes of operation (Native or Extended). In Native mode, 16 the stack operates in modulo 2 , and in Extended mode, it operates in modulo 2 ...

Page 13

Z ILOG Bits within a byte 16-bit word at address n: Least Significant Byte Most Significant Byte 32-bit word at address n: D7-0 (Least Significant Byte) D15-8 D23-16 D31-24 (Most Significant Byte) Memory addresses: Even address ...

Page 14

Z ILOG 2.5. EXTERNAL I/O ADDRESS SPACE External I/O address space is 4 Gbytes in size and External I/O addresses are generated by I/O instructions except those reserved for on-chip I/O address space accesses. It I/O Instruction IN A, (n) ...

Page 15

... THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MER- CHANTABILITY OR FITNESS FOR ANY PURPOSE. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. ...

Page 16

Z ILOG 2.1 INTRODUCTION The Z380 CPU supports five address spaces correspond- ing to the different types of locations that can be ad- dressed and the method by which the logical addresses are formed. These five address spaces are: CPU ...

Page 17

Z ILOG 2.2 CPU REGISTER SPACE (Continued) BCz DEz HLz IXz IYz BCz' DEz' HLz' IXz' IYz' Iz SPz PCz Figure 2-1. Register File Organization (Z380 MPU) 2-2 4 Sets of Registers ...

Page 18

Z ILOG 2.2.1 Primary and Working Registers The working register set is divided into two register files: the primary file and the alternate file (designated by prime (‘)). Each file contains an 8-bit accumulator (A), a Flag register (F), and ...

Page 19

Z ILOG 2.2.6 Stack Pointer (Continued) Increment/decrement of the Stack Pointer is affected by modes of operation (Native or Extended). In Native mode, 16 the stack operates in modulo 2 , and in Extended mode, it operates in modulo 2 ...

Page 20

Z ILOG Bits within a byte 16-bit word at address n: Least Significant Byte Most Significant Byte 32-bit word at address n: D7-0 (Least Significant Byte) D15-8 D23-16 D31-24 (Most Significant Byte) Memory addresses: Even address ...

Page 21

Z ILOG 2.5. EXTERNAL I/O ADDRESS SPACE External I/O address space is 4 Gbytes in size and External I/O addresses are generated by I/O instructions except those reserved for on-chip I/O address space accesses. It I/O Instruction IN A, (n) ...

Page 22

... THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MER- CHANTABILITY OR FITNESS FOR ANY PURPOSE. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. ...

Page 23

Z ILOG 3.1 INTRODUCTION ™ The Z380 CPU architecture allows access to 4 Gbytes memory addressing space, and 4G locations of I/O. It offers 16/32-bit manipulation capability while main- taining object-code compatibility with the Z80 CPU. ...

Page 24

Z ILOG 3.2 DECODER DIRECTIVES The Decoder Directive is not an instruction, but rather a directive to the instruction decoder. The instruction de- coder may be directed to fetch an additional byte or word of immediate data or address with ...

Page 25

... THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MER- CHANTABILITY OR FITNESS FOR ANY PURPOSE. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. ...

Page 26

Z ILOG 4.1 INSTRUCTION An instruction is a consecutive list of one or more bytes in memory. Most instructions act upon some data; the term operand refers to the data to be operated upon. For Z380 CPU instructions, operands can ...

Page 27

Z ILOG 4.2.2 Immediate (IM) (Continued) Instruction OPERATION OPERAND The operand value is in the instruction Immediate mode is often used to initialize registers. Also, this addressing mode is affected by the DDIR Immediate Data Directives to expand the immediate ...

Page 28

Z ILOG 4.2.4 Direct Address (DA) When Direct Address mode is used, the data processed is at the location whose memory or I/O port address is in the instruction. Instruction Memory or OPERATION I/O Port ADDRESS OPERAND The operand value ...

Page 29

Z ILOG 4.2.5 Indexed (X) When the Indexed addressing mode is used, the data processed is at the location whose address is the contents use, offset by an 8-bit signed displacement in the instruction. The ...

Page 30

Z ILOG 2. Load accumulator from location (IX-1) in Extended mode SETC XM ;Set Extended mode LD A, (IX-1) ;Load into the accumulator the ;contents of the memory location ;whose address is one less than ;the contents of IX Before ...

Page 31

Z ILOG 4.2.6 Program Counter Relative Mode (RA) (Continued) Before instruction execution After instruction execution Address calculation: In Native mode, –2 is encoded as 0FEH in the instruction, and it is sign extended to a 16-bit value before added to ...

Page 32

Z ILOG 4.2.7 Stack Pointer Relative Mode (SR) For Stack Pointer Relative addressing mode, the data processed is at the location whose address is the contents of the Stack Pointer, offset by an 8-bit displacement in the instruction. The Stack ...

Page 33

Z ILOG 4.2.7 Stack Pointer Relative Mode (SR) (Continued) 2. Load HL from location (SP – Extended mode, Long Word mode SETC XM ;In Extended mode DDIR LW ;operate next instruction in Long Word mode LD HL, (SP–4) ...

Page 34

... THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MER- CHANTABILITY OR FITNESS FOR ANY PURPOSE. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. ...

Page 35

Z ILOG 5.1 INTRODUCTION ™ The Z380 CPU instruction set is a superset of the Z80 CPU and the Z180 MPU; the Z380 CPU is opcode compatible with the Z80 CPU/Z180 MPU. Thus, a Z80/Z180 program can be executed on ...

Page 36

Z ILOG 5.2.1 Carry Flag (C) The Carry flag is set or cleared depending on the operation being performed. For add instructions that generate a carry and subtract instruction generating a borrow, the Carry flag is set to 1. The ...

Page 37

Z ILOG 5.2.7 Condition Codes The Carry, Zero, Sign, and Parity/Overflow flags are used to control the operation of the conditional instructions. The operation of these instructions is a function of the state of one of the flags. Special mnemonics ...

Page 38

Z ILOG 5.3 SELECT REGISTER The Select Register (SR) controls the register set selection and the operating modes of the Z380 CPU. The reserved bits in the SR are for future expansion; they will always read as zeros and should ...

Page 39

Z ILOG 5.3.8. Long Word Mode (LW) This bit controls the Long Word/Word mode selection for the Z380 CPU. This bit is set by the SETC LW instruction and cleared by the RESC LW instruction. When this bit is set, ...

Page 40

Z ILOG 5.5 INSTRUCTION SET FUNCTIONAL GROUPS This section presents an overview of the Z380 instruction set, arranged by functional groups. (See Section 5.5 for an explanation of the notation used in Tables 5-2 through 5- 11). 5.5.1 8-Bit Load/Exchange ...

Page 41

Z ILOG 5.5.2 16-Bit and 32-Bit Load, Exchange, SWAP, and PUSH/POP Group This group of load, exchange, and PUSH/POP instructions (Table 5-4) allows one or two words of data (two bytes equal one word transferred between registers and ...

Page 42

Z ILOG 5.5.2 16-Bit and 32-Bit Load, Exchange, SWAP and PUSH/POP Group (Continued) Table 5-6. Supported Source and Destination Combination for 16-Bit and 32-Bit Load Instructions. Source Destination ...

Page 43

Z ILOG has even number ( Word mode transfer, and a multiple of four in Long Word mode (D1 and D0 are both 0). Also, in Word or Long Word Block transfer, memory pointer ...

Page 44

Z ILOG 5.5.5 16-Bit Arithmetic Operation This group of instructions (Table 5-10) provide 16-bit arithmetic instructions. The Add, Add with Carry, Subtract, Subtract with Carry, AND, OR, Exclusive OR, and Com- pare takes one input operand from an addressing register ...

Page 45

Z ILOG 5.5.6 8-Bit Manipulation, Rotate and Shift Group Instructions in this group (Table 5-11) test, set, and reset bits within bytes, and rotate and shift byte data one bit position. Bits to be manipulated are specified by a field ...

Page 46

Z ILOG 5.5.8 Program Control Group This group of instructions (Table 5-13) affect the Program Counter (PC) and thereby control program flow. The CPU registers and memory are not altered except for the Stack Pointer and the Stack, which play ...

Page 47

Z ILOG 5.5.9 External Input/Output Instruction Group This group of instructions (Table 5-14) are used for trans- ferring a byte, a word, or string of bytes or words between peripheral devices and the CPU registers or memory. Byte I/O port ...

Page 48

Z ILOG 5.5.9 External Input/Output Instruction Group (Continued) Instruction Name Input Input Accumulator Input to Word-Wide Register Input Byte from Absolute Address Input Word from Absolute Address Input and Decrement (Byte) Input and Decrement (Word) Input, Decrement, and Repeat (Byte) ...

Page 49

Z ILOG 5.5.10 Internal I/O Instruction Group This group (Table 5-15) of instructions is used to access on-chip I/O addressing space on the Z380 CPU. This group consists of instructions for transferring a byte from/ to Internal I/O locations and ...

Page 50

Z ILOG 5.5.11 CPU Control Group The instructions in this group (Table 5-16) act upon the CPU control and status registers or perform other functions that do not fit into any of the other instruction groups. These include two instructions ...

Page 51

Z ILOG 5.5.12 Decoder Directives The Decoder Directives (Table 5-17) are a special instruc- tions to expand the Z80 instruction set to handle the Z380’s 4 Gbytes of linear memory addressing space. For details on this instruction, refer to Chapter ...

Page 52

Z ILOG 5.6 NOTATION AND BINARY ENCODING (Continued) Condition Codes. The following symbols describe the condition codes. Z Zero* NZ Not Zero* C Carry Carry* S Sign NS No Sign NV No Overflow V Overflow PE Parity Even ...

Page 53

Z ILOG Operation Byte Sequence B Memory Read 3-4 Memory Write 0-1 Internal I/O Read 3-4 Internal I/O Write 0-1 1X External I/O Read 4-5 1X External I/O Write 1-2 2X External I/O Read 9-11 2X External I/O Write 1-3 ...

Page 54

Z ILOG ADC ADD WITH CARRY (BYTE) ADC A,src src = R, RX, IM, IR, X Operation src + C The source operand together with the Carry flag is added to the accumulator and the sum is ...

Page 55

Z ILOG ADC HL,src Operation: HL(15-0) HL(15-0) + src(15- The source operand together with the Carry flag is added to the HL register and the sum is stored in the HL register. The contents of the source are ...

Page 56

Z ILOG ADCW ADD WITH CARRY (WORD) ADCW [HL,]src Operation: HL(15-0) HL(15-0) + src(15- The source operand together with the Carry flag is added to the HL register and the sum is stored in the HL register. The ...

Page 57

Z ILOG ADD A,src src = R, RX, IM, IR, X Operation src The source operand is added to the accumulator and the sum is stored in the accumulator. The contents of the source are unaffected. Two’s ...

Page 58

Z ILOG ADD ADD (WORD) ADD dst,src Operation: If (XM) then begin dst(31-0) dst(31-0) + src(31-0) end else begin dst(15-0) dst(15-0) + src(15-0) end The source operand is added to the destination and the sum is stored in the destination. ...

Page 59

Z ILOG ADD SP,src src = IM Operation: if (XM) then begin SP(31-0) end else begin SP(15-0) end The source operand is added to the SP register and the sum is stored in the SP register. This has the effect ...

Page 60

Z ILOG ADDW ADD (WORD) ADDW [HL,]src Operation: HL(15-0) HL(15-0) + src(15-0) The source operand is added to the HL register and the sum is stored in the HL register. The contents of the source are unaffected. Two’s complement addition ...

Page 61

Z ILOG AND [A,]src src = R, RX, IM, IR, X Operation AND src A logical AND operation is performed between the corresponding bits of the source operand and the accumulator and the result is stored in the ...

Page 62

Z ILOG ANDW AND (WORD) ANDW [HL,]src Operation: HL(15-0) HL(15-0) AND src(15-0) A logical AND operation is performed between the corresponding bits of the source operand and the HL register and the result is stored in the HL register. A ...

Page 63

Z ILOG BIT b,dst dst = R, IR, X Operation: Z NOT dst(b) The specified bit b within the destination operand is tested, and the Zero flag is set the specified bit is 0, otherwise the Zero ...

Page 64

Z ILOG BTEST BANK TEST BTEST Operation: S SR(16) Z SR(24) V SR(0) C SR(8) The Alternate Register bits in the Select Register (SR) are transferred to the flags. This allows the program to determine the state of the machine. ...

Page 65

Z ILOG CALL [cc,]dst Operation: if (cc is TRUE) then begin if (XM) then begin SP (SP) (SP+1) (SP+2) (SP+3) PC(31-0) else begin SP (SP) (SP+1) PC(15-0) end end A conditional Call transfers program control to the destination address if ...

Page 66

Z ILOG CALR CALL RELATIVE CALR [cc,]dst Operation: if (cc is true) then begin dst if (XM) then begin SP (SP) (SP+1) (SP+2) (SP+3) PC(31-0) end else begin SP (SP) (SP+1) PC(15-0) end end A conditional Call transfers program control ...

Page 67

Z ILOG CCF Operation: C NOT C The Carry flag is inverted. Flags: S: Unaffected Z: Unaffected H: The previous state of the Carry flag V: Unaffected N: Cleared C: Set if the Carry flag was clear before the operation; ...

Page 68

Z ILOG CP COMPARE (BYTE) CP [A,]src src = R, RX, IM, IR, X Operation: A – src The source operand is compared with the accumulator and the flags are set accordingly. The contents of the accumulator and the source ...

Page 69

Z ILOG CPW [HL,]src Operation: HL(15-0) – src(15-0) The source operand is compared with the HL register and the flags are set accordingly. The contents of the HL register and the source are unaffected. Two’s complement subtraction is performed. Flags: ...

Page 70

Z ILOG CPD COMPARE AND DECREMENT (BYTE) CPD Operation (HL) if (XM) then begin HL(31-0) end else begin HL(15-0) end BC(15-0) This instruction is used for searching strings of byte data. The byte of data at the location ...

Page 71

Z ILOG CPDR Operation: Repeat until (BC=0 OR match) begin A - (HL) if (XM) then begin HL(31-0) end else begin HL(15-0) end BC(15-0) end This instruction is used for searching strings of byte data. The bytes of data starting ...

Page 72

Z ILOG CPI COMPARE AND INCREMENT (BYTE) CPI Operation (HL) if (XM) then begin HL(31-0) end else begin HL(15-0) end BC(15-0) This instruction is used for searching strings of byte data. The byte of data at the location ...

Page 73

Z ILOG CPIR Operation: Repeat until (BC=0 OR match) begin A - (HL) if (XM) then begin HL(31-0) end else begin HL(15-0) end BC(15-0) end This instruction is used for searching strings of byte data. The bytes of data starting ...

Page 74

Z ILOG CPL COMPLEMENT ACCUMULATOR CPL [A] Operation: A NOT A The contents of the accumulator are complemented (one's complement); all 1s are changed to 0 and vice-versa. Flags: S: Unaffected Z: Unaffected H: Set V: Unaffected N: Set C: ...

Page 75

Z ILOG CPLW [HL] Operation: HL(15-0) NOT HL(15-0) The contents of the HL register are complemented (ones complement); all 1s are changed to 0 and vice-versa. Flags: S: Unaffected Z: Unaffected H: Set V: Unaffected N: Set C: Unaffected Addressing ...

Page 76

Z ILOG DAA DECIMAL ADJUST ACCUMULATOR DAA Operation: A Decimal Adjust A The accumulator is adjusted to form two 4-bit BCD digits following a binary, two’s complement addition or subtraction on two BCD-encoded bytes. The table below indicates the operation ...

Page 77

Z ILOG DDIR mode mode = Operation: None, decoder directive only This is not an instruction, but rather a directive to the instruction decoder. The instruction decoder may be directed to fetch an additional ...

Page 78

Z ILOG DEC DECREMENT (BYTE) DEC dst dst = R, RX, IR, X Operation: dst dst – 1 The destination operand is decremented by one and the result is stored in the destination. Two’s complement subtraction is performed. Flags: S: ...

Page 79

Z ILOG DEC[W] dst dst = R, RX Operation: if (XM) then begin dst(31-0) end else begin dst(15-0) end The destination operand is decremented by one and the result is stored in the destination. Two’s complement subtraction is performed. Note ...

Page 80

Z ILOG DI DISABLE INTERRUPTS DI [n] Operation present) then begin for i begin if (n( then begin IER(i-1) end end if (n( then begin SR(5) end end else begin SR(5) ...

Page 81

Z ILOG DIVUW [HL,]src Operation: HL(15- src HL(31-16) remainder The contents of the the HL register (dividend) are divided by the source operand (divisor) and the quotient is stored in the lower word of the HL register; the ...

Page 82

Z ILOG DJNZ DECREMENT AND JUMP IF NON-ZERO DJNZ dst dst = RA Operation <> 0) then begin dst if (XM) then begin PC(31-0) end else begin PC(15-0) end end The B register is decremented by one. ...

Page 83

Z ILOG EI [n] Operation present) then begin for i begin if (n( then begin IER(i-1) end end if (n( then begin SR(5) end end else begin SR(5) end If an ...

Page 84

Z ILOG EX EXCHANGE ACCUMULATOR/FLAG WITH ALTERNATE BANK EX AF,AF’ Operation: SR(0) NOT SR(0) Bit 0 of the Select Register (SR), which controls the selection of primary or alternate bank for the accumulator and flag register, is complemented, thus effectively ...

Page 85

Z ILOG EXCHANGE ADDRESSING REGISTER WITH TOP OF STACK EX (SP),dst Operation: if (LW) then begin (SP+3) dst(31-24) (SP+2) dst(23-16) end (SP+1) dst(15-8) (SP) dst(7-0) The contents of the destination register are exchanged with the top of the stack. In ...

Page 86

Z ILOG EX EXCHANGE REGISTER (WORD) EX dst,src dst = R, RX src = R, RX Operation: if (LW) then begin dst(31-0) end else begin dst(15-0) end The contents of the destination are exchanged with the contents of the source. ...

Page 87

Z ILOG EXCHANGE REGISTER WITH ALTERNATE REGISTER (BYTE) EX dst,src src = R Operation: dst src The contents of the destination are exchanged with the contents of the source, where the destination is a register in the primary bank and ...

Page 88

Z ILOG EX EXCHANGE REGISTER WITH ALTERNATE REGISTER (WORD) EX dst,src src = R, RX Operation: if (LW) then begin dst(31-0) end else begin dst(15-0) end The contents of the destination are exchanged with the contents of the source, where ...

Page 89

Z ILOG EX A,src src = R, IR Operation: dst src The contents of the accumulator are exchanged with the contents of the source. Flags: S: Unaffected Z: Unaffected H: Unaffected V: Unaffected N: Unaffected C: Unaffected Addressing Mode Syntax ...

Page 90

Z ILOG EXALL EXCHANGE ALL REGISTERS WITH ALTERNATE BANK EXALL Operation: SR(24) NOT SR(24) SR(16) NOT SR(16) SR(8) NOT SR(8) Bits 8, 16, and 24 of the Select Register (SR), which control the selection of primary or alternate bank for ...

Page 91

Z ILOG EXTS [A] Operation (A(7)=0) then begin H ¨ 00h if (LW) then begin HL(31-16) end end else begin H ¨ FFh if (LW) then begin HL(31-16) end end The contents of the accumulator, considered as a ...

Page 92

Z ILOG EXTSW EXTEND SIGN (WORD) EXTSW [HL] Operation: If (HL(15)=0) then begin HL(31-16) end else begin HL(31-16) end The contents of the low word of the HL register, considered as a signed, two's complement integer, are sign-extended to 32 ...

Page 93

Z ILOG EXX Operation: SR(8) NOT SR(8) Bit 8 of the Select Register (SR), which controls the selection of primary or alternate bank for the BC, DE, and HL registers, is complemented, thus effectively exchanging the BC, DE, and HL ...

Page 94

Z ILOG EXXX EXCHANGE IX REGISTER WITH ALTERNATE BANK EXXX Operation: SR(16) NOT SR(16) Bit 16 of the Select Register (SR), which controls the selection of primary or alternate bank for the IX register, is complemented, thus effectively exchanging the ...

Page 95

Z ILOG EXXY Operation: SR(24) NOT SR(24) Bit 24 of the Select Register (SR), which controls the selection of primary or alternate bank for the IY register, is complemented, thus effectively exchanging the IY register between the two banks. Flags: ...

Page 96

Z ILOG HALT HALT HALT Operation: CPU Halts The CPU operation is suspended until either an interrupt request or reset request is received. This instruction is used to synchronize the CPU with external events, preserving its state until an interrupt ...

Page 97

Z ILOG Operation: SR(4-3) p The interrupt mode of operation is set to one of four modes. (See Chapter 6 for a description of the various modes for responding to interrupts). The ...

Page 98

Z ILOG IN INPUT (BYTE) IN dst,(C) dst = R Operation: dst (C) The byte of data from the selected peripheral is loaded into the destination register. During the I/O transaction, the contents of the 32-bit BC register are placed ...

Page 99

Z ILOG INW dst,(C) dst = R Operation: dst(15-0) (C) The word of data from the selected peripheral is loaded into the destination register. During the I/O transaction, the contents of the 32-bit BC register are placed on the address ...

Page 100

Z ILOG IN INPUT ACCUMULATOR IN A,(n) Operation: A (n) The byte of data from the selected peripheral is loaded into the accumulator. During the I/O transaction, the 8-bit peripheral address from the instruction is placed on the low byte ...

Page 101

Z ILOG IN0 dst,(n) dst = R Operation: dst (n) The byte of data from the selected on-chip peripheral is loaded into the destination register. No external I/O transaction will be generated as a result of this instruction, although the ...

Page 102

Z ILOG INA INPUT DIRECT FROM PORT ADDRESS (BYTE) INA A,(nn) Operation: A (nn) The byte of data from the selected peripheral is loaded into the accumulator. During the I/O transaction, the peripheral address from the instruction is placed on ...

Page 103

Z ILOG INAW HL,(nn) Operation: HL(15-0) (nn) The word of data from the selected peripheral is loaded into the HL register. During the I/O transaction, the peripheral address from the instruction is placed on the address bus. Any bytes of ...

Page 104

Z ILOG INC INCREMENT (BYTE) INC dst dst = R, RX, IR, X Operation: dst dst + 1 The destination operand is incremented by one and the sum is stored in the destination. Two’s complement addition is performed. Flags: S: ...

Page 105

Z ILOG INC[W] dst dst = R, RX Operation: if (XM) then begin dst(31-0) end else begin dst(15-0) end The destination operand is incremented by one and the sum is stored in the destination. Two’s complement addition is performed. Note ...

Page 106

Z ILOG IND INPUT AND DECREMENT (BYTE) IND Operation: (HL) ( – – 1 This instruction is used for block input of strings of data. During the I/O transaction the 32- bit BC register is ...

Page 107

Z ILOG INDW Operation: (HL) (DE) BC(15-0) BC(15-0) – – 2 This instruction is used for block input of strings of data. During the I/O transaction the 32- bit DE register is placed on the address bus. ...

Page 108

Z ILOG INDR INPUT, DECREMENT AND REPEAT (BYTE) INDR Operation: repeat until (B=0) begin (HL) ( – – 1 end This instruction is used for block input of strings of data. The string of input ...

Page 109

Z ILOG INDRW Operation: repeat until (BC=0) begin (HL) BC(15-0) HL end This instruction is used for block input of strings of data. The string of input data from the selected peripheral is loaded into memory at consecutive addresses, starting ...

Page 110

Z ILOG INI INPUT AND INCREMENT (BYTE) INI Operation: (HL) ( – This instruction is used for block input of strings of data. During the I/O transaction the 32- bit BC register is ...

Page 111

Z ILOG INIW Operation: (HL) (DE) BC(15-0) BC(15-0) – This instruction is used for block input of strings of data. During the I/O transaction the 32-bit DE register is placed on the address bus. First ...

Page 112

Z ILOG INIR INPUT, INCREMENT AND REPEAT (BYTE) INIR Operation: repeat until (B=0) begin (HL) ( – end This instruction is used for block input of strings of data. The string of input ...

Page 113

Z ILOG INIRW Operation: repeat until (BC=0) begin (HL) BC(15-0) HL end This instruction is used for block input of strings of data. The string of input data from the selected peripheral is loaded into memory at consecutive addresses, starting ...

Page 114

Z ILOG JP JUMP JP [cc,]dst Operation: if (cc is TRUE) then begin if (XM) then begin PC(31-0) end else begin PC(15-0) end end A conditional jump transfers program control to the destination address if the setting of a selected ...

Page 115

Z ILOG JR [cc,]dst Operation: if (cc is TRUE) then begin dst SIGN EXTEND dst if (XM) then begin PC(31-0) end else begin PC(15-0) end end A conditional Jump transfers program control to the destination address if the setting of ...

Page 116

Z ILOG LD LOAD ACCUMULATOR LD dst,src Operation: dst src The contents of the source are loaded into the destination. S: Unaffected Flags: Z: Unaffected H: Unaffected V: Unaffected N: Unaffected C: Unaffected Load into Accunulator Addressing Mode Syntax LD ...

Page 117

Z ILOG LD dst,n dst = R, RX, IR, X Operation: dst n The byte of immediate data is loaded into the destination. Flags: S: Unaffected Z: Unaffected H: Unaffected V: Unaffected N: Unaffected C: Unaffected Addressing Mode Syntax LD ...

Page 118

Z ILOG LD LOAD IMMEDIATE (WORD) LD dst,nn dst = R, RX Operation: if (LW) then begin dst(31-0) end else begin dst(15-0) end The word of immediate data is loaded into the destination. Flags: S: Unaffected Z: Unaffected H: Unaffected ...

Page 119

Z ILOG LDW dst,nn dst = IR Operation: if (LW) then begin dst(31-0) end else begin dst(15-0) end The word of immediate data is loaded into the destination. Flags: S: Unaffected Z: Unaffected H: Unaffected V: Unaffected N: Unaffected C: ...

Page 120

Z ILOG LD LOAD REGISTER (BYTE) LD dst,src dst = R src = R, RX, IM, IR dst = R, RX, IR, X src = R Operation: dst src The contents of the source are loaded into the ...

Page 121

Z ILOG LD[W] dst,src dst = R src = R, RX, IR, DA dst = R, RX, IR, DA src = R Operation: if (LW) then begin dst(31-0) end else begin dst(15-0) end The contents of ...

Page 122

Z ILOG LD[W] LOAD REGISTER (WORD) Load from Register Addressing Mode Syntax RX: LD RX,R LD IX,IY LD IY,IX IR: LD (IR),RR LD (IR),RX DA: LD (nn),HL LD (nn),R LD (nn), (XY+d),R LD (IY+d),IX LD (IX+d),IY LD (SP+d),R ...

Page 123

Z ILOG LD dst,src dst = SP src = R, RX, IM, DA dst = DA src = SP Operation: if (LW) then begin dst(31-0) end else begin dst(15-0) end The contents of the source are loaded into the destination. ...

Page 124

Z ILOG LD LOAD FROM REGISTER (BYTE) LD dst,src dst = A src = I, R Operation: dst src The contents of the source are loaded into the accumulator. The contents of the source are not affected. ...

Page 125

Z ILOG LD dst,src dst = I, R src = A Operation: dst src The contents of the accumulator are loaded into the destination. Note that the R register does not contain the refresh address and is not modified by ...

Page 126

Z ILOG LD[W] LOAD I REGISTER (WORD) LD[W] dst,src Operation: if (LW) then begin dst(31-0) end else begin dst(15-0) end The contents of the source are loaded into the destination S: Unaffected Flags: Z: Unaffected H: Unaffected V: Unaffected N: ...

Page 127

Z ILOG LDCTL dst,src Operation: if (dst = SR) then begin SR(31-24) SR(23-16) SR(15-8) end else begin dst end The contents of the source are loaded into the destination. S: Unaffected Flags: Z: Unaffected H: Unaffected V: Unaffected N: Unaffected ...

Page 128

Z ILOG LDCTL LOAD FROM CONTROL REGISTER (WORD) LDCTL dst,src Operation: if (LW) then begin dst(31-0) end else begin dst(15-0) end The contents of the Select Register (SR) are loaded into the HL register. Flags: S: Unaffected Z: Unaffected H: ...

Page 129

Z ILOG LDCTL dst,src Operation: if (LW) then begin dst(31-16) end else begin dst(31-24) dst(23-16) end dst(15-8) dst(0) The contents of the HL register are loaded into the Select Register (SR). If Long Word mode is not in effect the ...

Page 130

Z ILOG LDD LOAD AND DECREMENT (BYTE) LDD Operation: (DE) (HL – – 1 BC(15-0) BC(15-0) – 1 This instruction is used for block transfers of strings of data. The byte of data at the ...

Page 131

Z ILOG LDDW Operation: if (LW) then begin (DE) (DE+1) (DE+2) (DE+ BC(15-0) end else begin (DE) (DE+ BC(15-0) end This instruction is used for block transfers of words of data. The word of data at ...

Page 132

Z ILOG LDDR LOAD, DECREMENT AND REPEAT (BYTE) LDDR Operation: repeat until BC=0 begin (DE BC(15-0) end This instruction is used for block transfers of strings of data. The bytes of data at the location addressed by the ...

Page 133

Z ILOG LDDRW Operation: repeat until (BC=0) begin if (LW) then begin (DE) (DE+1) (DE+2) (DE+ BC(15-0) end else begin (DE) (DE+ BC(15-0) end end This instruction is used for block transfers of strings of data. ...

Page 134

Z ILOG LDI LOAD AND INCREMENT (BYTE) LDI Operation: (DE) (HL BC(15-0) BC(15-0) – 1 This instruction is used for block transfers of strings of data. The byte of data at the ...

Page 135

Z ILOG LDIW Operation: if (LW) then begin (DE) (DE+1) (DE+2) (DE+ BC(15-0) end else begin (DE) (DE+ BC(15-0) end This instruction is used for block transfers of words of data. The word of data at ...

Page 136

Z ILOG LDIR LOAD, INCREMENT AND REPEAT (BYTE) LDIR Operation: repeat until (BC=0) begin (DE BC(15-0) end This instruction is used for block transfers of strings of data. The bytes of data at the location addressed by the ...

Page 137

Z ILOG LDIRW Operation: repeat until (BC=0) begin if (LW) then begin (DE) (DE+1) (DE+2) (DE+ BC(15-0) end else begin (DE) (DE+ BC(15-0) end end This instruction is used for block transfers of strings of data. ...

Page 138

Z ILOG MLT MULTIPLY UNSIGNED (BYTE) MLT R src = R Operation: R(15-0) R(7-0) x R(15-8) The contents of the upper byte of the source register are multiplied by the contents of the lower byte of the source register and ...

Page 139

Z ILOG MTEST Operation: S SR(7) Z SR(6) C SR(1) The three mode control bits in the Select Register (SR) are transferred to the flags. This allows the program to determine the state of the machine. Flags: S: Set if ...

Page 140

Z ILOG MULTW MULTIPLY (WORD) MULTW [HL,]src Operation: HL(31-0) HL(15-0) x src(15-0) The contents of the HL register are multiplied by the source operand and the product is stored in the HL register. The contents of the source are unaffected. ...

Page 141

Z ILOG MULTUW [HL,]src Operation: HL(31-0) HL(15-0) x src(15-0) The contents of the HL register are multiplied by the source operand and the product is stored in the HL register. The contents of the source are unaffected. Both operands are ...

Page 142

Z ILOG NEG NEGATE ACCUMULATOR NEG [A] Operation The contents of the accumulator are negated, that is replaced by its two’s complement value. Note that 80h is replaced by itself, because in two’s complement representation the negative number ...

Page 143

Z ILOG NEGW [HL] Operation: HL(15-0) -HL(15-0) The contents of the HL register are negated, that is replaced by its two’s complement value. Note that 8000h is, replaced by itself, because in two’s complement representation the negative number with the ...

Page 144

Z ILOG NOP NO OPERATION NOP Operation: None No operation. Flags: S: Unaffected Z: Unaffected H: Unaffected V: Unaffected N: Unaffected C: Unaffected Addressing Mode Syntax Instruction Format NOP 00000000 5-110 U Execute Time Note 2 DC-8297-03 Z380 ™ ' ...

Page 145

Z ILOG OR [A,]src Operation src A logical OR operation is performed between the corresponding bits of the source operand and the accumulator and the result is stored in the accumulator bit is stored wherever ...

Page 146

Z ILOG ORW OR (WORD) ORW [HL,]src Operation: HL(15-0) HL(15-0) OR src(15-0) A logical OR operation is performed between the corresponding bits of the source operand and the HL register and the result is stored in the HL register. A ...

Page 147

Z ILOG OTDM Operation: (C) (HL – – – 1 This instruction is used for block output of strings of data to on-chip peripherals. No external I/O transaction will be generated as ...

Page 148

Z ILOG OTDMR OUTPUT, DECREMENT MEMORY REPEAT OTDMR Operation: repeat until (B=0) begin (C) (HL – – – 1 end This instruction is used for block output of strings of data to ...

Page 149

Z ILOG OTDR Operation: repeat until (B=0) begin B B – 1 (C) (HL – 1 end This instruction is used for block output of strings of data. The string of output data is loaded into the selected ...

Page 150

Z ILOG OTDRW OUTPUT, DECREMENT AND REPEAT (WORD) OTDRW Operation: repeat until (BC=0) begin BC(15-0) (DE) HL end This instruction is used for block output of strings of data. The string of output data is loaded into the selected peripheral ...

Page 151

Z ILOG OTIM Operation: (C) (HL – This instruction is used for block output of strings of data to on-chip peripherals. No external I/O transaction will be generated as ...

Page 152

Z ILOG OTIMR OUTPUT, INCREMENT MEMORY REPEAT OTIMR Operation: repeat until (B=0) begin (C) (HL – end This instruction is used for block output of strings of data to ...

Page 153

Z ILOG OTIR Operation: repeat until (B=0) begin B B – 1 (C) (HL end This instruction is used for block output of strings of data. The string of output data is loaded into the selected ...

Page 154

Z ILOG OTIRW OUTPUT, INCREMENT AND REPEAT (WORD) OTIRW Operation: repeat until (BC=0) begin BC(15-0) (DE) HL end This instruction is used for block output of strings of data. The string of output data is loaded into the selected peripheral ...

Page 155

Z ILOG OUT (C),src src = R, IM Operation: (C) src The byte of data from the source is loaded into the selected peripheral. During the I/O transaction, the contents of the 32-bit BC register are placed on the address ...

Page 156

Z ILOG OUTW OUTPUT (WORD) OUTW (C),src src = R, IM Operation: (C) src(15-0) The word of data from the source is loaded into the selected peripheral. During the I/O transaction, the contents of the 32-bit BC register are placed ...

Page 157

Z ILOG OUT (n),A Operation: (n) A The byte of data from the accumulator is loaded into the selected peripheral. During the I/O transaction, the 8-bit peripheral address from the instruction is placed on the low byte of the address ...

Page 158

Z ILOG OUT0 OUTPUT (TO PAGE 0) OUT0 (n),src src = R Operation: (n) src The byte of data from the source register is loaded into the selected on-chip peripheral. No external I/O transaction will be generated as a result ...

Page 159

Z ILOG OUT (nn),A Operation: (nn) A The byte of data from the accumulator is loaded into the selected peripheral. During the I/O transaction, the peripheral address from the instruction is placed on the address bus. Any bytes of address ...

Page 160

Z ILOG OUTAW OUTPUT DIRECT TO PORT ADDRESS (WORD) OUT (nn),HL Operation: (nn) HL(15-0) The word of data from the HL register is loaded into the selected peripheral. During the I/O transaction, the peripheral address from the instruction is placed ...

Page 161

Z ILOG OUTD Operation (C) (HL This instruction is used for block output of strings of data. During the I/O transaction the 32-bit BC register is placed on the address bus. Note ...

Page 162

Z ILOG OUTDW OUTPUT AND DECREMENT (WORD) OUTDW Operation: BC(15-0) BC(15- (DE) (HL This instruction is used for block output of strings of data. During the I/O transaction the 32- bit DE register is ...

Page 163

Z ILOG OUTI Operation (C) (HL This instruction is used for block output of strings of data. During the I/O transaction the 32- bit BC register is placed on the address bus. ...

Page 164

Z ILOG OUTIW OUTPUT AND INCREMENT (WORD) OUTIW Operation: BC(15-0) BC(15-0) –1 (DE) (HL This instruction is used for block output of strings of data. During the I/O transaction the 32- bit DE register is placed ...

Page 165

Z ILOG POP dst dst = AF Operation: F (SP) A (SP+ (LW) then begin end The contents of the memory location addressed by the Stack Pointer (SP) are loaded into ...

Page 166

Z ILOG POP POP CONTROL REGISTER POP dst dst = SR Operation: if (LW) then begin dst(6-0) dst(15-8) dst(23-16) dst(31-24) SP end else begin dst(6-0) dst(15-8) dst(23-16) dst(31-24) SP end The contents of the memory location addressed by the Stack ...

Page 167

Z ILOG POP dst dst = R, RX Operation: if (LW) then begin dst(7-0 ) dst(15-8) dst(23-16) dst(31-24) SP end else begin dst(7-0) dst(15-8) SP end The contents of the memory location addressed by the Stack Pointer (SP) are loaded ...

Page 168

Z ILOG PUSH PUSH ACCUMULATOR PUSH src src = AF Operation: if (LW) then begin (SP) F (SP+1) A (SP+2) 00h (SP+3) 00h end else begin (SP) F (SP+1) A end The ...

Page 169

Z ILOG PUSH src src = SR Operation: if (LW) then begin (SP) src(7-0) (SP+1) src(15-8) (SP+2) src(23-16) (SP+3) src(31-24) end else begin (SP) src(7-0) (SP+1) src(15-8) end The Stack Pointer (SP) ...

Page 170

Z ILOG PUSH PUSH IMMEDIATE PUSH src src = IM Operation: if (LW) then begin (SP) src(7-0) (SP+1) src(15-8) (SP+2) src(23-16) (SP+3) src(31-24) end else begin (SP) src(7-0) (SP+1) src(15-8) end The ...

Page 171

Z ILOG PUSH src src = R, RX Operation: if (LW) then begin (SP) src(7-0) (SP+1) src(15-8) (SP+2) src(23-16) (SP+3) src(31-24) end else begin (SP) src(7-0) (SP+1) src(15-8) end The Stack Pointer ...

Page 172

Z ILOG RES RESET BIT RES b, dst dst = R, IR, X Operation: dst(b) 0 The specified bit b within the destination operand is cleared to 0. The other bits in the destination are unaffected. The bit to be ...

Page 173

Z ILOG RESC mode mode = LCK, LW Operation: if (mode = LCK) then begin SR(1) 0 end else begin SR(6) 0 end When reseting Lock mode (LCK), the LCK bit (bit 1) in the Select Register (SR) is set ...

Page 174

Z ILOG RET RETURN RET [cc] Operation: if (cc is TRUE) then begin if (XM) then begin PC(7-0) PC(15-8) PC(23-16) PC(31-24) SP end else begin PC(7-0) PC(15-8) SP end end This instruction is used to return to a previously executing ...

Page 175

Z ILOG Operation: PC (31-0) SPC (31-0) This instruction is used to return to a previously executing procedure at the end of a breakpoint. The contents of the Shadow Program Counter (SPC), which holds the address of the next instruction ...

Page 176

Z ILOG RETI RETURN FROM INTERRUPT RETI Operation: if (XM) then begin PC(7-0) PC(15-8) PC(23-16) PC(31-24) SP end else begin PC(7-0) PC(15-8) SP end This instruction is used to return to a previously executing procedure at the end of a ...

Page 177

Z ILOG RETN Operation: if (XM) then begin PC(7-0) PC(15-8) PC(23-16) PC(31-24) SP end else begin PC(7-0) PC(15-8) SP end IEF1 This instruction is used to return to a previously executing procedure at the end of a procedure entered by ...

Page 178

Z ILOG RL ROTATE LEFT (BYTE) RL dst dst = R, IR, X Operation: tmp dst dst( dst(7) dst(n+1) tmp(n) for The contents of the destination operand are concatenated with the Carry flag ...

Page 179

Z ILOG RLW dst dst = R, RX, IR, X Operation: tmp dst dst( dst(15) dst(n+1) tmp(n) for The contents of the destination operand are concatenated with the Carry flag and together they ...

Page 180

Z ILOG RLA ROTATE LEFT (ACCUMULATOR) RLA Operation: tmp A A( A(7) A(n+1) tmp(n) for The contents of the accumulator are concatenated with the Carry flag and together they are rotated left one ...

Page 181

Z ILOG RLC dst dst = R, IR, X Operation: tmp dst C dst(7) dst(0) tmp(7) dst(n+1) tmp(n) for The contents of the destination operand are rotated left one bit position. Bit 7 of the ...

Page 182

Z ILOG RLCW ROTATE LEFT CIRCULAR (WORD) RLCW dst dst = R, RX, IR, X Operation: tmp dst C dst(15) dst(0) tmp(15) dst(n+1) tmp(n) for The contents of the destination operand are rotated left one ...

Page 183

Z ILOG RLCA Operation: tmp A C A(7) A(0) tmp(7) A(n+1) tmp(n) for The contents of the accumulator are rotated left one bit position. Bit 7 of the accumulator is moved to the bit 0 ...

Page 184

Z ILOG RLD ROTATE LEFT DIGIT RLD Operation: tmp(3-0) A(3-0) A(3-0) dst(7-4) dst(7-4) dst(3-0) dst(3-0) tmp(3-0) The low digit of the accumulator is logically concatenated to the destination byte whose memory address is in the HL register. The resulting three-digit ...

Page 185

Z ILOG RR dst dst = R, IR, X Operation: tmp dst dst( dst(0) dst(n) tmp(n+1) for The contents of the destination operand are concatenated with the Carry flag and together they are ...

Page 186

Z ILOG RRW ROTATE RIGHT (WORD) RRW dst dst = R, RX, IR, X Operation: tmp dst C dst(0) dst(15) C dst(n) tmp(n+1) for The contents of the destination operand are concatenated with the Carry ...

Page 187

Z ILOG RRA Operation: tmp A A( A(0) A(n) tmp(n+1) for The contents of the accumulator are concatenated with the Carry flag and together they are rotated right one bit position. Bit 0 ...

Page 188

Z ILOG RRC ROTATE RIGHT CIRCULAR (BYTE) RRC dst dst = R, IR, X Operation: tmp dst C dst(0) dst(7) tmp(0) dst(n) tmp(n+1) for The contents of the destination operand are rotated right one bit ...

Page 189

Z ILOG RRCW dst dst = R, RX, IR, X Operation: tmp dst C dst(0) dst(15) tmp(0) dst(n) tmp(n+1) for The contents of the destination operand are rotated right one bit position. Bit 0 of ...

Page 190

Z ILOG RRCA ROTATE RIGHT CIRCULAR (ACCUMULATOR) RRCA Operation: tmp A C A(0) A(7) tmp(0) A(n) tmp(n+1) for The contents of the accumulator are rotated right one bit position. Bit 0 of the accumulator is ...

Page 191

Z ILOG RRD Operation: tmp(3-0) A(3-0) A(3-0) dst(3-0) dst(3-0) dst(7-4) dst(7-4) tmp(3-0) The low digit of the accumulator is logically concatenated to the destination byte whose memory address is in the HL register. The resulting three-digit quantity is rotated to ...

Page 192

Z ILOG RST RESTART RST address Operation: if (XM) then begin (SP) PC(7-0) (SP+1) PC(15-8) (SP+2) PC(23-16) (SP+3) PC(31-24) end else begin (SP) PC(7-0) (SP+1) PC(15-8) end PC address The current Program ...

Page 193

Z ILOG SBC A,src src = R, RX, IM, IR, X Operation src - C The source operand together with the Carry flag is subtracted from the accumulator and the difference is stored in the accumulator. The ...

Page 194

Z ILOG SBC HL,src dst = HL src = BC, DE, HL, SP Operation: HL(15-0) HL(15-0) - src(15- The source operand together with the Carry flag is subtracted from the HL register and the difference is stored in ...

Page 195

Z ILOG SBCW SUBTRACT WITH CARRY (WORD) SBCW [HL,]src Operation: HL(15-0) HL(15-0) - src(15- The source operand together with the Carry flag is subtracted from the HL register and the difference is stored in the HL register. The ...

Page 196

Z ILOG SCF SET CARRY FLAG SCF Operation The Carry flag is set to 1. Flags: S: Unaffected Z: Unaffected H: Cleared V: Unaffected N: Cleared C: Set Addressing Mode Syntax Instruction Format SCF 00110111 5-162 U Execute ...

Page 197

Z ILOG SET b, dst dst = R, IR, X Operation: dst(b) 1 The specified bit b within the destination operand is set to 1. The other bits in the destination are unaffected. The bit to be set is specified ...

Page 198

Z ILOG SETC SET CONTROL BIT SETC mode mode = LCK, LW, XM Operation: if (mode = LCK) then begin SR(1) 1 end else if (mode = LW) then begin SR(6) 1 end else begin SR(7) 1 end When setting ...

Page 199

Z ILOG SLA dst dst = R, IR, X Operation: tmp dst C dst(7) dst(0) 0 dst(n+1) tmp(n) for The contents of the destination operand are shifted left one bit position. Bit 7 of the ...

Page 200

Z ILOG SLAW SHIFT LEFT ARITHMETIC (WORD) SLAW dst dst = R, RX, IR, X Operation: tmp dst dst( dst(15) dst(n+1) tmp(n) for The contents of the destination operand are shifted left one ...