Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 74

• Manufacturer Part Number: Z8038018FSG
• Description: IC 16 BIT Z80 MPU 100-QFP
• Manufacturer: Zilog

Specifications of Z8038018FSG

• Processor Type: Z380
• Features: 16-Bit, High-Performance Enhanced Z80 CPU
• Speed: 18MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z80380x
• Core: Z380
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 18 MHz
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16/32 BIT ARITHMETIC AND LOGICAL GROUP (Continued)
Mnemonic
ADDW [HL,]nn
ADDW [HL,]XY
ADDW [HL,](XY+d)
ADCW [HL,]uu
SUBW [HL,]uu
SBCW [HL,]uu
ANDW [HL,]uu
ORW [HL,]uu
XORW [HL,]uu
CPW [HL,]uu
ADD HL, (nn)
SUB HL, (nn)
uu is any of rr, nn, t, (IX+d), (IY+d) as shown for ADDW instruction. The indicated bits replace the (000) is the ADD set
above.
Notes:
Instructions in Italic face are Z380 new instructions, instructions with underline are Z180 original instructions.
I:
X1: In Extend mode, this instruction operates in 32-bits;
This instruction may be used with DDIR Immediate instructions.
src(31-0)
dd
00
01
10
11
Pair
BC
DE
HL
SP
src(31-0) opr dst(31-0)
Symbolic
Operation
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL - uu
HL
HL
pp
00
01
11
HL + nn
HL+XY
HL+(XY+d)
HL+uu+CY
HL-uu
HL - uu - CY
HL AND uu
HL OR uu
HL XOR uu
HL+(nn)
HL- (nn)
Pair
BC
DE
HL
Flags
S Z x H x V N C
• • x
• • x
qq
00
01
11
x
x
x
x
x
x
x 1 x P 0 0
x 0 x P 0 0
x 0 x P 0 0
x
x V 0
x V 0
x V 0
x V 0
x V 1
x V 1
x V 1
x • 0
x • 0
Pair
BC
DE
SP
P/
0
y
1
76 543 210 HEX Bytes Time Notes
11 101 101
10 (000) 110
11 y11
10 (000) 111
11 y11
11 (000) 110
11 101 101
11 010 110
11 101 101
11 010 110
Opcode
(010)
(001)
(011)
(100)
(110)
(101)
(111)
n
n
n
n
n
n
XY
IX
IY
101
101
ED
C6
ED
C6
ED
D6
86
87
# of
4
2
4
4
4
Page 74 of 125
4+r
2+r
2+r
Execute
2
2
I, X1
I, X1
I
I
I