Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 112

• Manufacturer Part Number: Z8038018FSG
• Description: IC 16 BIT Z80 MPU 100-QFP
• Manufacturer: Zilog

Specifications of Z8038018FSG

• Processor Type: Z380
• Features: 16-Bit, High-Performance Enhanced Z80 CPU
• Speed: 18MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z80380x
• Core: Z380
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 18 MHz
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RESET
The Z380 MPU is placed in a dormant state when the
/RESET input is asserted. All its operations are terminated,
including any interrupt, bus request or bus transaction that
may be in progress. Its IOCLK goes Low on the next
BUSCLK rising edge, and enters into the BUSCLK divided-
down-by-eight mode. The address and data buses are tri-
stated, and the bus control signals are driven to their
inactive states. The effect of a reset on the Z380 CPU and
related I/O registers is depicted in Table 6, and the effect
on the on-chip peripheral functions is summarized in
Table 8.
The /RESET input may be asynchronous to BUSCLK,
though it is sampled internally at BUSCLK’s falling edges.
For proper initialization of the Z380 MPU, V
within operating specification and its BUSCLK must be
stable for more than five cycles with /RESET held Low. The
/RESET input has a built-in Schmitt trigger buffer to facili-
tate power-on reset generation through an RC network.
DD
must be
Note that if a user system has devices external to the Z380
MPU that are clocked by IOCLK, these devices may
require a /RESET pulse width that spans over a number of
IOCLK cycles (now at BUSCLK/8) for proper initialization.
The Z380 MPU proceeds to fetch its first instruction 3.5
BUSCLK cycles after /RESET is deasserted, provided
such deassertion meets the proper setup and hold times
with reference to the falling edge of BUSCLK, as depicted
in Figure 20 in the External Interface Section. Figure 19 in
the same section indicates a synchronization of IOCLK
when /RESET is deasserted. Again with the proper setup
and hold times being met, IOCLK’s first rising edge is 11.5
BUSCLK cycles after the /RESET deassertion, preceded
by a minimum of 4 BUSCLK cycles where IOCLK is at Low.
Note that if /BREQ is active when /RESET is deasserted, the
Z380 MPU would relinquish the bus instead of fetching its
first instruction. IOCLK synchronization would still take
place as described before.
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