Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 92

• Manufacturer Part Number: Z8038018FSG
• Description: IC 16 BIT Z80 MPU 100-QFP
• Manufacturer: Zilog

Specifications of Z8038018FSG

• Processor Type: Z380
• Features: 16-Bit, High-Performance Enhanced Z80 CPU
• Speed: 18MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z80380x
• Core: Z380
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 18 MHz
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Trap and Break Register
Reserved bits 7-2. Some of these bits are reserved for
breakpoint functions, including a Break-on-Halt feature.
TF (Trap on Instruction Fetch). TF goes active to logic 1
when an undefined opcode fetched in the instruction
stream is detected. TF can be reset under program control
by writing it with a logic 0. However, it cannot be written with
a logic 1.
Trap Interrupt
The Z380 MPU generates a trap when an undefined
opcode is encountered. The trap is enabled immediately
after reset, and it is not maskable. This feature can be used
to increase software reliability or to implement extended
instructions. An undefined opcode can be fetched from
the instruction stream, or it can be returned as a vector in
an interrupt acknowledge transaction in interrupt mode 0.
When a trap occurs, the Z380 MPU operates as follows.
1. The TF or TV bit in the Assigned Vectors Base and Trap
2. If the undefined opcode was fetched from instruction
Register goes active, to indicate the source of the
undefined opcode.
stream, the starting address of the trap causing in-
struction is pushed onto the stack. (Note that the
starting address of a decoder directive preceding an
instruction encoding is considered the starting ad-
dress of the instruction.)
TRPBK: 00000019H
R/W
7
--
0
--
0
--
0
Figure 27. Trap and Break Register
--
0
--
0
0
--
TF
0
Refer to the Z380 ICE specifications for details. Read as 0s,
should write to as 0s.
TV (Trap on Interrupt Vector). TV goes active to logic 1
when an undefined opcode is returned as a vector in an
interrupt acknowledge transaction in mode 0. TV can be
reset under program control by writing it with a logic 0.
However, it cannot be written with a logic 1.
3. The states of IEF1 and IEF2 are cleared.
4. The Z380 MPU commences to fetch and execute
Note that instruction execution resumes at address 0,
similar to the occurrence of a reset. Testing the TF and TV
bits in the Assigned Vectors Base and Trap Register will
distinguish the two events. Even if trap handling is not in
place, repeated restarts from address 0 is an indicator of
possible illegal instructions at system debugging.
TV
If the undefined opcode was a returned interrupt
vector (in interrupt mode 0), the interrupted PC value
is pushed onto the stack.
instructions from address 00000000H.
0
0
Reset Value
Trap on Interrupt Vector
Reserved
Program as 0
Read as 0
Trap on Instruction Fetch
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