Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 115

IC 16 BIT Z80 MPU 100-QFP

Z8038018FSG

Manufacturer Part Number
Z8038018FSG
Description
IC 16 BIT Z80 MPU 100-QFP
Manufacturer
Zilog
Datasheets

Specifications of Z8038018FSG

Processor Type
Z380
Features
16-Bit, High-Performance Enhanced Z80 CPU
Speed
18MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
100-QFP
Processor Series
Z80380x
Core
Z380
Program Memory Size
64 KB
Maximum Clock Frequency
18 MHz
Operating Supply Voltage
0 V to 5 V
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z8038018FSG
Manufacturer:
Zilog
Quantity:
10 000
AC CHARACTERISTICS
Z380
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Notes:
1.
2.
3.
4.
5.
Applicable for Data Bus and /MSIZE inputs
/BREQ can also be asserted/deasserted asynchronously
External waits asserted at /WAIT input
Tx01(02)
Tx01(03)
Symbol
TcC
TwCh
TwCl
TrC
TfC
TdCf(BCr)
TdCr(BCf)
TdBCr(OUT)
TdBCf(OUT)
TsIN(BCr)
ThIN(BCr)
TsBR(BCf)
ThBR(BCf)
TsMW(BCr)
ThMW(BCr)
TsMW(BCf)
ThMW(BCf)
TsIOW(BCr)
ThIOW(BCr)
TsIOW(BCf)
ThIOW(BCf)
TwNMI1
TwRES1
Tx01(02)
Tx01(03)
Version
=
or
=
or
[Output 1] TdBCr(OUT) - [Output 2] TdBCr(OUT)
[Output 1] TdBCf(OUT) - [Output 2] TdBCf(OUT)
[Output 1] TdBCr(OUT) - [Output 3] TdBCf(OUT)
[Output 1] TdBCf(OUT) - [Output 3] TdBCr(OUT)
Parameter
CLK Cycle Time
CLK Width High
CLK Width Low
CLK Rise Time
CLK Fall Time
CLK Fall to BUSCLK Rise Delay
CLK Rise to BUSCLK Fall Delay
BUSCLK Rise to Output Valid Delay
BUSCLK Fall to Output Valid Delay
Input to BUSCLK Rise Setup Time
Input to BUSCLK Rise Hold Time
/BREQ to BUSCLK Fall Setup Time
/BREQ to BUSCLK Fall Hold Time
Mem Wait to BUSCLK Rise Setup Time
Mem Wait to BUSCLK Rise Hold Time
Mem Wait to BUSCLK Fall Setup Time
Mem Wait to BUSCLK Fall Hold Time
IO Wait to BUSCLK Rise Setup Time
IO Wait to BUSCLK Rise Hold Time
IO Wait to BUSCLK Fall Setup Time
IO Wait to BUSCLK Fall Hold Time
/NMI Low Width
Reset Low Width
Output Skew (Same Clock Edge)
Output Skew (Opposite Clock Edge)
Min
55
24.5
24.5
16
0
16
0
16
0
24
0
24
0
24
0
25
10
–3
–2
Z8038018
Max
3
3
30
27
6.5
6.5
+2
+3
Page 115 of 125
Note
1
1
2
2
3
3
3
3
3
3
3
3
4
5

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