Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 52

• Manufacturer Part Number: Z8038018FSG
• Description: IC 16 BIT Z80 MPU 100-QFP
• Manufacturer: Zilog

Specifications of Z8038018FSG

• Processor Type: Z380
• Features: 16-Bit, High-Performance Enhanced Z80 CPU
• Speed: 18MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z80380x
• Core: Z380
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 18 MHz
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Z380 Microprocessor
Product Specification
This flag is set when an add instruction generates a carry or a subtract instruc-
Carry (C).
tion generates a borrow. Certain logical, rotate and shift instructions affect the Carry flag.
Add/Subtract (N).
This flag is used by the Decimal Adjust Accumulator instruction to
distinguish between add and subtract operations. The flag is set for subtract operations and
cleared for add operations.
During arithmetic operations this flag is set to indicate a two’s
Parity/Overflow (P/V).
complement overflow. During logical and rotate operations, this flag is set to indicate even
parity of the result or cleared to indicate odd parity.
This flag is set if an 8-bit arithmetic operation generates a carry or borrow
Half Carry (H).
between bits 3 and 4, or if a 16-bit operation generates a carry or borrow between bits 11
and 12, or if a 32-bit operation generates a carry or borrow between bits 27 and 28. This
bit is used to correct the result of a packed BCD addition or subtract operation.
This flag is set if the result of an arithmetic or logical operation is a zero.
Zero (Z).
This flag stores the state of the most significant bit of the accumulator.
Sign (S).
Index Registers
The four index registers, IX, IX’, IY and IY’, each hold a 32-bit base address that is used
in the Indexed addressing mode. The Index registers can also function as general-purpose
registers with the upper and lower byte of the lower 16 bits being accessed individually.
These byte registers are called IXU, IXU’, IXL and IXL’ for the IX and IX’ registers, and
IYU, IYU’, IYL and IYL’ for the IY and IY’ registers.
Interrupt Register
The Interrupt register (I) is used in interrupt modes 2 and 3 for /INT0 to generate a 32-bit
indirect address to an interrupt service routine. The I register supplies the upper twenty-
four or sixteen bits of the indirect address and the interrupting peripheral supplies the
lower eight or sixteen bits. In the Assigned Vectors mode for /INT1-3 the upper sixteen
bits of the vector are supplied by the I register; bits 15-9 are the assigned vector base and
bits 8-0 are the assigned vector unique to each of /INT1-3.
Program Counter
The Program Counter (PC) is used to sequence through instructions in the currently exe-
cuting program and to generate relative addresses. The PC contains the 32-bit address of
the current instruction being fetched from memory. In the Native mode, the PC is effec-
tively only 16 bits long, as carries from bit 15 to bit 16 are inhibited in this mode. In
Extended mode, the PC is allowed to increment across all 32 bits.
R Register
The R register can be used as a general-purpose 8-bit read/write register. The R register is
not associated with the refresh controller and its contents are changed only by the user.
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