Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 12

• Manufacturer Part Number: Z8038018FSG
• Description: IC 16 BIT Z80 MPU 100-QFP
• Manufacturer: Zilog

Specifications of Z8038018FSG

• Processor Type: Z380
• Features: 16-Bit, High-Performance Enhanced Z80 CPU
• Speed: 18MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z80380x
• Core: Z380
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 18 MHz
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Z380 Microprocessor
Product Specification
Transactions
A transaction is initiated by the bus master and is responded to by some other device on
the bus. Only one transaction can proceed at a time; six kinds of transactions can occur:
Memory, Refresh, I/O, Interrupt Acknowledge, RETI (Return from Interrupt), and Halt.
The Z380 MPU is unique in that memory and I/O bus transactions use separate control
signals. This allows the memory interface to be optimized independently of the I/O inter-
face.
Memory Transactions
Memory transactions move instructions or data to or from memory when the Z380 MPU
performs a memory access. Thus, they are generated during program execution to fetch
instructions from memory and to fetch and store memory data. They are also generated to
store old program status and fetch new program status during interrupt and trap handling,
and are used by DMA peripherals to transfer information. A memory transaction is two
clock cycles long unless extended with wait states. Wait states may be inserted between
each of the four T states in a memory transaction and are one BUSCLK cycle long per
wait state. The external /WAIT input is sampled only after any internally-generated wait
states are inserted. Memory transactions may transfer either bytes or words. If the Z380
MPU attempts to transfer a word to a byte-wide memory, the /MSIZE signal should be
asserted Low to force this transaction to be byte-wide dynamically. The Z380 MPU will
then perform another memory transaction to transfer the byte that was not transferred dur-
ing the first transaction.
Read memory transactions are shown without wait states, with wait states between T1 and
T2, between T2 and T3, and between T3 and T4 (Figures 3 - 6). The data bus is driven by
the memory being addressed, and the memory data is latched immediately before the ris-
ing edge of BUSCLK which terminates T4.
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PS010002-0708