Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 53

• Manufacturer Part Number: Z8038018FSG
• Description: IC 16 BIT Z80 MPU 100-QFP
• Manufacturer: Zilog

Specifications of Z8038018FSG

• Processor Type: Z380
• Features: 16-Bit, High-Performance Enhanced Z80 CPU
• Speed: 18MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z80380x
• Core: Z380
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 18 MHz
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Z380 Microprocessor
Product Specification
Stack Pointer
The Stack Pointer (SP) is used for saving information when an interrupt or trap occurs and
for supporting subroutine calls and returns. Stack Pointer relative addressing allows
parameter passing using the SP.
Select Register
The Select Register (SR) controls the register set selection and the operating modes of the
Z380 CPU. The reserved bits in the SR are for future expansion; they will always read as
zeros and should be written with zeros for future compatibility. The SR is shown in
Figure 34.
Addressing Modes
Addressing modes are used by the Z380 CPU to calculate the effective address of an oper-
and needed for execution of an instruction. Seven addressing modes are supported by the
Z380 CPU. Of these seven, one is an addition to the Z80 CPU addressing modes (Stack
Pointer Relative) and the remaining six modes are either existing or extensions to the Z80
CPU addressing modes.
The operand is one of the 8-bit registers (A, B, C, D, E, H, L, IXU, IXL, IYU,
Register.
IYL, A', B', C', D', E', H' or L'); or is one of the 16-bit or 32-bit registers (BC, DE, HL, IX,
IY, BC', DE', HL', IX', IY' or SP) or one of the special registers (I or R).
Immediate.
The operand is in the instruction itself and has no effective address. The
DDIR IB and DDIR IW decoder directives allow specification of 24-bit and 32-bit imme-
diate operands, respectively.
The contents of a register specify the effective address of an operand.
Indirect Register.
The HL register is the primary register used for memory accesses, but BC and DE can also
be used. (For the JP instruction, IX and IY can also be used for indirection.) The BC regis-
ter is used for I/O space accesses.
Direct Address.
The effective address of the operand is the location whose address is
contained in the instruction. Depending on the instruction, the operand is either in the I/O
or memory address space. Sixteen bits of direct address is the norm, but the DDIR IB and-
DDIR IW decoder directives allow 24-bit and 32-bit direct addresses, respectively.
Indexed.
The effective address of the operand is the location computed by adding the
two's-complement signed displacement contained in the instruction to the contents of the
IX or IY register. Eight bits of index is the norm, but the DDIR IB and DDIR IW decoder
directives allow 16-bit and 24-bit indexes, respectively.
An 8-, 16-or 24-bit displacement contained in the instruc-
Program Counter Relative.
tion is added to the Program Counter to generate the effective address. This mode is avail-
able only for Jump and Call instructions.
Page 53 of 125
PS010002-0708