Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 32

• Manufacturer Part Number: Z8038018FSG
• Description: IC 16 BIT Z80 MPU 100-QFP
• Manufacturer: Zilog

Specifications of Z8038018FSG

• Processor Type: Z380
• Features: 16-Bit, High-Performance Enhanced Z80 CPU
• Speed: 18MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z80380x
• Core: Z380
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 18 MHz
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Z380 Microprocessor
Product Specification
IOCLK
ADDRESS
DAT A
/WAIT
/MI
/IORQ
/IORD
/IOWR
/INTAK
Figure 22. Interrupt Acknowledge Cycle, /INT3-1
An interrupt acknowledge transaction for /INT0 is five IOCLK cycles long unless
extended by Wait states. /WAIT is sampled at two separate points during the transaction.
/WAIT is first sampled at the end of the first IOCLK cycle during the transaction. Wait
states inserted here allow the external daisy-chain between peripherals with a longer time
to settle before the interrupt vector is requested. /WAIT is then sampled at the end of the
fourth IOCLK cycle to delay the point at which the interrupt vector is read by the Z380
MPU, after it has been requested.
The interrupt vector may be either eight or sixteen bits, under program control, and is
latched by the falling edge of IOCLK in the last cycle of the interrupt acknowledge trans-
action. When using Mode 0 interrupts, where the Z380 MPU fetches an instruction from
the interrupting device, these fetches are always eight bits wide and are transferred over
D7-D0.
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