Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 113

• Manufacturer Part Number: Z8038018FSG
• Description: IC 16 BIT Z80 MPU 100-QFP
• Manufacturer: Zilog

Specifications of Z8038018FSG

• Processor Type: Z380
• Features: 16-Bit, High-Performance Enhanced Z80 CPU
• Speed: 18MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z80380x
• Core: Z380
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 18 MHz
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register
Program Counter
Stack Pointer
I
R
Select Register
A and F Registers
Register Extensions
I/O Bus Control Register 0
Interrupt Enable Register
Assigned Vector Base Register
Trap and Break Register
Peripheral Functions
Memory Chip Selects and Waits
I/O Waits
DRAM Refresh Controller
Standby Mode
Table 7. Effect of a Reset on Z380 CPU and Related I/O Registers
Table 8. Effect of a Reset on On-chip Peripheral Functions
Reset Value
00000000
00000000
000000
00000000
0000
Reset Conditions
Lower Memory Chip Select Signal enabled for lowest 1 MBytes
Upper Memory Chip Select Signal enabled for highest
Midrange Memory Chip Select Signal and waits disabled.
External I/O read, write -- 7 waits.
RETI -- 3 waits.
Interrupt daisy chain -- 7 waits.
Disabled
Disabled
(00000000H-000FFFFFH), with 7 T1, 3 T2, and 7 T3 waits.
16th MBytes (00F00000H - 00FFFFFFH),
with 7 T1, 3 T2, and 7 T3 waits.
00
00
01
00
00
Comments
PCz, PC
SPz, SP
Iz, I
Register Bank 0 Selected:
AF, Main Bank, IX, IY
Native Mode
Maskable Interrupts Disabled, in Mode 0
Bus Request Lock-Off
Register Banks 3-0:
A, F, A’, F’ Unaffected
Register Bank 0:
BCz, DEz, HLz, IYz,
BCz’, DEz’, HLz’, IYz’
(All “non-extended” portions unaffected.)
Register Bank 3-1 Unaffected.
IOCLK = BUSCLK/8
/INT0 Enabled
Page 113 of 125