Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 90

• Manufacturer Part Number: Z8038018FSG
• Description: IC 16 BIT Z80 MPU 100-QFP
• Manufacturer: Zilog

Specifications of Z8038018FSG

• Processor Type: Z380
• Features: 16-Bit, High-Performance Enhanced Z80 CPU
• Speed: 18MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z80380x
• Core: Z380
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 18 MHz
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Interrupt Control
The Z380 MPU’s flags and registers associated with inter-
rupt processing are listed in Table 4. As discussed in the
CPU Architecture section, some of the registers reside in
IEF1, IEF2
IEF1 controls the overall enabling and disabling of all on-
chip peripheral and external maskable interrupt requests.
If IEF1 is at logic 0, all such interrupts are disabled. The
purpose of IEF2 is to correctly manage the occurrence of
/NMI. When /NMI is acknowledged, the state of IEF1 is
copied to IEF2 and then IEF1 is cleared to logic 0. At the
Note:
NC = No Change
I, I Extend
The 8-bit Interrupt Register and the 16-bit Interrupt
Register Extension are cleared during reset.
Names
Interrupt Enable Flags
Interrupt Register
Interrupt Register Extension
Interrupt Enable Register
Assigned Vectors Base Register
Trap and Break Register
Operation
/RESET
Trap
/NMI
RETN
/INT3-/INT0
RETI
RET
EI
DI
LD A,I or LD R,I
LD HL,I
Table 4. Operation Effects on IEF1 and IEF2
IEF1
0
0
0
IEF2
0
NC
NC
1
0
NC
NC
Table 3. Interrupt Flags and Registers
IEF2
0
0
IEF1
NC
0
NC
NC
1
0
NC
NC
Mnemonics
IEF1, IEF2
I
Iz
IER
AVBR
TRPBK
the on-chip I/O address space and can be accessed only
with reserved on-chip I/O instructions.
end of the /NMI interrupt service routine, execution of the
Return From Nonmaskable Interrupt instruction, RETN,
automatically copies the state of IEF2 back to IEF1. This is
a means to restore the interrupt enable condition existing
before the occurrence of /NMI. Table 5 summarizes the
states of IEF1 and IEF2 resulting from various operations.
Comments
Inhibits all interrupts except Trap and /NMI.
Disables interrupt nesting.
IEF1 value copied to IEF2, then IEF1 is cleared.
Returns from /NMI service routine.
Disables interrupt nesting.
Returns from service routine, Z80 I/O device.
Returns from service routine, non-Z80 I/O device.
IEF2 value is copied to P/V Flag.
Access Methods
EI and DI instructions
LD I,A and LD A,I instructions
LD I,HL and LD HL,I instructions
On-chip I/O instructions, addr
00000017H, EI and DI instructions
On-chip I/O instructions, addr
00000018H
On-chip I/O instructions, addr
00000019H
(accessing both Iz and I)
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