CY8CTMG200-16LGXIT Cypress Semiconductor Corp, CY8CTMG200-16LGXIT Datasheet - Page 92

• Manufacturer Part Number: CY8CTMG200-16LGXIT
• Description: IC MCU 32K FLASH 16-COL
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG200-16LGXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 13
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.2
The following registers are associated with the TrueTouch Module and are listed in address order. The register descriptions
have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are
reserved bits and are not detailed in the register descriptions that follow. Always write reserved bits with a value of ‘0’. For a
complete table of TrueTouch Module registers, refer to the
11.2.1
The TrueTouch Control Register 0 (CS_CR0) controls the
operation of the TrueTouch counters. Do not write bits [7:1]
while the block is enabled.
Bits 7 and 6: CSOUT[1:0]. These bits select between a
number of TrueTouch signals that can be driven to an output
pin. Refer to
register on page
Bit 5: CSD_PRSCLK. This bit selects between IMO-P or
the PRS output as a clock source to drive the main capacitor
switch. ‘0’ selects IMO-P. ‘1’ selects PRS output.
Bit 4: CSD_CS_CLK. This bit selects between IMO or
IMO-P for the TrueTouch counters to work. Depending on
this bit selection, either IMO or IMO-P is sent as the source
clock to the clock dividers, which generate CS_CLK as
shown in
selects IMO-P.
Bit 3: CSD_MODE. This bit enables the CSD mode. When
this bit is enabled, the TIMER1 block works on the IMO-P
(pre-scaled IMO) clock. This is also an enable for TrueTouch
counters to toggle.
‘0’ disables CSD mode. Programmable Timer1 works on
either CPUCLK/CLK32, (depending on CLKSEL bit selec-
tion in the PT1_CFG (0, B3h) register). ‘1’ enables CSD
mode.
When this bit is set to ‘1’, the Programmable Timer1 works
on IMO-P.
Note : Once the CSD_MODE bit is enabled, the IMO-P clock
is a free running divider clock that cannot be stopped and re-
TrueTouch Module
92
0,A0h
CSOUT[1:0]
Address
00
01
10
11
Figure 11-13 on page
Register Definitions
CS_CR0
CS_CR0 Register
IN
CS_INT
COL
COH
Figure 11-13 on page 91
Name
273.
Bit 7
CSOUT[1:0]
Description
91. ‘0’ selects IMO. ‘1’
Bit 6
and to the
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
PRSCLK
CSD_
Bit 5
OUT_P1
CSD_CS_
TrueTouch Register Summary on page
Bit 4
CLK
started. The IMO-P and the CPU clock are both derived from
the IMO clock but the phase relationship between them is
nondeterministic.
Bits 2 and 1: MODE[1:0]. These bits specify the operating
mode of the counter logic. The modes are shown in the fol-
lowing table.
Bit 0: EN. When this bit is written to ‘1’, the counters are
enabled for counting. When this bit is written to ‘0’, counting
is stopped and all counter values are reset to zero. If the
counting mode is stopped in conjunction with an event (see
MODE[1:0]), the current count is held and read from the
counter registers. Toggle the EN bit to ‘0’ and then back to
‘1’ to start a new count.
For additional information, refer to the
page
MODE[1:0]
00
01
10
11
211.
MODE
CSD_
Bit 3
Stop On Event
In this mode, the block starts counting when the EN bit is
set, and stops counting upon the selected interrupt event.
This mode allows the user to read the counter results in
firmware. Counting is restarted again by disabling and re-
enabling the block using the EN bit.
Pulse Width
In this mode, after the EN bit is set, the block waits for a
positive edge upon the data input selection to start the
counter, and then stops the counter upon the following neg-
ative edge of the data input. Polarity is adjusted with the
INV bit (CS_CR1). Counting is restarted by disabling and
re-enabling the block using the EN bit.
Period
In this mode, after the EN bit is set, the block waits for a
positive edge upon the data input selection to start the
counter, and then stops the counter upon the following pos-
itive edge of the data input. Polarity is adjusted with the INV
bit (CS_CR1). Counting is restarted by disabling and re-
enabling the block using the EN bit.
Continuous
In this mode, the counter is used to generate a periodic
interrupt. The period is set by the input clock selection in
conjunction with using one 8-bit counter (period=100h) or
the chained 16-bit counter (period = 10000h).
Bit 2
MODE[1:0]
Bit 1
Description
84.
CS_CR0 register on
Bit 0
EN
Access
RW : 00
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