CY8CTMG200-16LGXIT Cypress Semiconductor Corp, CY8CTMG200-16LGXIT Datasheet - Page 177

• Manufacturer Part Number: CY8CTMG200-16LGXIT
• Description: IC MCU 32K FLASH 16-COL
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG200-16LGXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 13
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.3.10
The Endpoint Control Register 0 (EPx_CR0) is used for sta-
tus and configuration of the non-control endpoints 1 to 8.
Bit 7: Stall. When this bit is set, the SIE stalls an OUT
packet if the mode bits are set to ACK-OUT. The SIE stalls
an IN packet if the mode bits are set to ACK-IN. This bit
must be cleared for all other modes. ‘0‘ is do not issue a
stall. ‘1‘ is stall an OUT packet if mode bits are set to ACK-
OUT, or stall an IN packet if mode bits are set to ACK-IN.
Bit 5: NAK Int Enable. When set, this bit causes an end-
point interrupt to be generated even when a transfer com-
pletes with a NAK. ‘0‘ is do not issue an interrupt after
completing the transaction by sending NAK. ‘1‘ is interrupt
after transaction is complete by sending NAK.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Address
1,54h
1,55h
1,56h
1,57h
1,58h
1,59h
1,5Ah
1,5Bh
EP1_CR0
EP2_CR0
EP3_CR0
EP4_CR0
EP5_CR0
EP6_CR0
EP7_CR0
EP8_CR0
EPx_CR0 Register
Name
Bit 7
Stall
Stall
Stall
Stall
Stall
Stall
Stall
Stall
Bit 6
NAK_INT_EN
NAK_INT_EN
NAK_INT_EN
NAK_INT_EN
NAK_INT_EN
NAK_INT_EN
NAK_INT_EN
NAK_INT_EN
Bit 5
ACK’ed Tx
ACK’ed Tx
ACK’ed Tx
ACK’ed Tx
ACK’ed Tx
ACK’ed Tx
ACK’ed Tx
ACK’ed Tx
Bit 4
Bit 4: ACK’ed Transaction. The ACK'ed Transaction bit is
set whenever the SIE engages in a transaction to the regis-
ter's endpoint that completes with an ACK packet. This bit is
cleared by any writes to the register. ‘0‘ is no ACK'ed trans-
actions since bit was last cleared. ‘1‘ indicates a transaction
ended with an ACK.
Bits 3 to 0: Mode[3:0]. The mode controls how the USB
SIE responds to traffic and how the USB SIE changes the
mode of that endpoint as a result of host packets to the end-
point. Refer to
Endpoints” on page
For additional information, refer to the
page
265.
Bit 3
“Mode Encoding for Control and Non-Control
Bit 2
166.
Mode[3:0]
Mode[3:0]
Mode[3:0]
Mode[3:0]
Mode[3:0]
Mode[3:0]
Mode[3:0]
Mode[3:0]
Bit 1
EPx_CR0 register on
Bit 0
Full-Speed USB
Access
# : 00
# : 00
# : 00
# : 00
# : 00
# : 00
# : 00
# : 00
177
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