CY8CTMG200-16LGXIT Cypress Semiconductor Corp, CY8CTMG200-16LGXIT Datasheet - Page 41

• Manufacturer Part Number: CY8CTMG200-16LGXIT
• Description: IC MCU 32K FLASH 16-COL
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG200-16LGXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 13
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ISR, the ISR is also required to restore the value before exe-
cuting the RETI instruction.
When the upper bit of the PgMode bits is set to ‘1‘, all nor-
mal memory access is forced to the SRAM page indicated
by the CUR_PP register value.
PgMode bit values and the corresponding Memory Paging
mode.
4.1.6
The Source Indexed and Destination Indexed addressing
modes to SRAM are treated as a unique addressing mode
in a PSoC device with more than one page of SRAM. An
example of an indexed addressing mode is the MOV A,
[X+expr] instruction. Register access has indexed
addressing as well; however, those instructions are not
affected by the SRAM paging architecture.
Important Note
program a PSoC device, be aware that the compiler writer
may restrict the use of some memory paging modes.
Review the conventions in your compiler’s user guide for
more information on restrictions or conventions associated
with memory paging modes.
Indexed SRAM accesses operate in one of three modes:
■
■
■
The mode is determined by the value of the PgMode bits in
the CPU_F register. However, the final SRAM page that is
used also requires setting either the Stack Page Pointer
(STK_PP) register or the Index Page Pointer (IDX_PP) reg-
ister. The table below shows the three indexed memory
access modes. The third column of the table is provided for
reference only.
Table 4-1. CPU_F PgMode Bit Modes
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
00b
01b
10b
11b
*
PgMode BIts
Mode used by SROM functions initiated by the SSC instruction.
CPU_F
Index memory access modes are forced to SRAM
Page 0.
Index memory access modes are directed to the SRAM
page indicated by the value in the STK_PP register.
Index memory access is forced to the SRAM page indi-
cated by the value in the IDX_PP register.
SRAM Page
Index Memory Page Pointer
CUR_PP
CUR_PP
Current
INT_CLR2
0
0
SRAM Page
STK_PP
Indexed
STK_PP
IDX_PP
If you are not using assembly to
0
Table 4-1
ISR*
ISR with variables on stack
summarizes the
Typical Use
After reset, the PgMode bits are set to 00b. In this mode,
index memory accesses are forced to SRAM Page 0, just as
they are in a PSoC device with only 256 bytes of SRAM.
This mode is also automatically enabled when an interrupt
occurs in a PSoC device and is considered the default ISR
mode. This is because before the ISR is entered, the M8C
pushes the current value of the CPU_F register onto the
stack and then clears the CPU_F register. Thus, by default,
any indexed memory access in an ISR is guaranteed to
occur in SRAM Page 0. When the RETI instruction executes
to end the ISR, the previous value of the CPU_F register is
restored as is the previous page mode. Note that this ISR
behavior is the default and that the PgMode bits in the
CPU_F register may be changed while in an ISR. If the
PgMode bits are changed while in an ISR, the pre-ISR value
is still restored by the RETI; but if the STK_PP or IDX_PP
registers are changed in the ISR, the ISR is also required to
restore the values before executing the RETI instruction.
The most likely PgMode bit change, while in an ISR, is from
the default value of 00b to 01b. In the 01b mode, indexed
memory access is directed to the SRAM page indicated by
the value of the STK_PP register. By using the PgMode,
modification of the STK_PP register value is unnecessary.
The STK_PP register determines on which SRAM page the
stack is located. The 01b paging mode is intended to pro-
vide easy access to the stack, while in an ISR, by setting the
CPU_X register (just X in instruction format) equal to value
of SP using MOV X, SP instruction.
The two previous paragraphs covered two of the three
indexed memory access modes: STK_PP and forced to
SRAM Page 0. Note, as shown in
STK_PP mode for indexed memory access is available
under two PgMode settings. The 01b mode is intended for
ISR use and the 11b mode is intended for non-ISR use. The
third indexed memory access mode requires the PgMode
bits to be set to 10b. In this mode indexed memory access is
forced to the SRAM page indicated by the value of the
IDX_PP register.
Table
4-1, that the
RAM Paging
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