CY8CTMG200-16LGXIT Cypress Semiconductor Corp, CY8CTMG200-16LGXIT Datasheet - Page 145

• Manufacturer Part Number: CY8CTMG200-16LGXIT
• Description: IC MCU 32K FLASH 16-COL
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG200-16LGXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 13
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

This chapter presents the Serial Peripheral Interconnect (SPI) and its associated registers. For a complete table of the SPI
registers, refer to the
isters in address order, refer to the
18.1
The Serial Peripheral Interconnect (SPI) block is a dedi-
cated master or slave SPI. The SPI slave function requires
three inputs: Clock, Data, and SS_ (unless the SS_ is forced
active with the SS_bit in the configuration register).
Figure 18-1. SPI Block Diagram
18.1.1
The SPI is a Motorola™ specification for implementing full-
duplex synchronous serial communication between devices.
The 3-wire protocol uses both edges of the clock to enable
synchronous communication without the need for stringent
setup and hold requirements.
signals in a simple connection.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
18. SPI
MOSI,
MISO
SCLK
CONFIGURATION[7:0]
TRANSMIT[7:0]
DATA_IN
CLK_IN
SYSCLK
Architectural Description
SS_
SPI Protocol Function
SPI Block
Registers
Summary Table of the System Resource Registers on page
DATA_OUT
CLK_OUT
CONTROL[7:0]
RECEIVE[7:0]
INT
Figure 18-2
MOSI,
SCLK
MISO
Register Reference chapter on page
shows the basic
Figure 18-2. Basic SPI Configuration
A device can be a master or slave. A master outputs clock
and data to the slave device and inputs slave data. A slave
device inputs clock and data from the master device and
outputs data for input to the master. Together, the master
and slave are essentially a circular Shift register, where the
master generates the clocking and initiates data transfers.
A basic data transfer occurs when the master sends eight
bits of data, along with eight clocks. In any transfer, both
master and slave transmit and receive simultaneously. If the
master only sends data, the received data from the slave is
ignored. If the master wishes to receive data from the slave,
the master must send dummy bytes to generate the clocking
for the slave to send data back.
Data is output by
both the Master
one edge of the
and Slave on
187.
clock.
SCLK
MISO
MOSI
MISO
SPI Master
106. For a quick reference of all PSoC reg-
MOSI
SCLK
SS_
input of both devices on the
MOSI
SCLK
SS_
opposite edge of the clock.
SPI Slave
Data is registered at the
MISO
145
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