CY8CTMG200-16LGXIT Cypress Semiconductor Corp, CY8CTMG200-16LGXIT Datasheet - Page 24

• Manufacturer Part Number: CY8CTMG200-16LGXIT
• Description: IC MCU 32K FLASH 16-COL
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG200-16LGXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 13
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section B: PSoC Core
Core Register Summary
This table lists all the PSoC registers for the CPU core in address order within their system resource configuration. The
grayed out bits are reserved bits. If you write these bits always write them with a value of ‘0’. For the core registers, the first ‘x’
in some register addresses represents either bank 0 or bank 1. These registers are listed throughout this manual in bank 0,
even though they are also available in bank 1.
Summary Table of the Core Registers
24
x,F7h
x,6Ch
x,6Dh
x,6Eh
x,6Fh
0,D0h
0,D1h
0,D3h
0,D4h
0,D5h
0,DAh
0,DBh
0,DCh
0,DEh
0,DFh
0,E0h
0,E1h
0,E2h
0,00h
0,01h
0,04h
0,05h
0,08h
0,09h
0,0Ch
0,0Dh
1,00h
1,01h
1,04h
1,05h
1,08h
1,09h
1,0Ch
1,0Dh
0,10h
0,11h
1,10h
1,11h
Address
CPU_F
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
CUR_PP
STK_PP
IDX_PP
MVR_PP
MVW_PP
INT_CLR0
INT_CLR1
INT_CLR2
INT_MSK2
INT_MSK1
INT_MSK0
INT_SW_EN
INT_VC
PRT0DR
PRT0IE
PRT1DR
PRT1IE
PRT2DR
PRT2IE
PRT3DR
PRT3IE
PRT0DM0
PRT0DM1
PRT1DM0
PRT1DM1
PRT2DM0
PRT2DM1
PRT3DM0
PRT3DM1
PRTxDR
PRTxIE
PRTxDM0
PRTxDM1
Name
Endpoint3
Endpoint3
Bit 7
I2C
I2C
PgMode[1:0]
Endpoint2
Endpoint2
Sleep
Sleep
Bit 6
GENERAL PURPOSE I/O (GPIO) REGISTERS (page 59)
INTERRUPT CONTROLLER REGISTERS (page 45)
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
RAM PAGING (SRAM) REGISTERS (page 39)
Endpoint1
USB_WAKE Endpoint8
USB
Wakeup
Endpoint1
XIO_1
Bit 5
SPI
SPI
M8C REGISTER (page 27)
Endpoint0
Endpoint8
Endpoint0
GPIO
GPIO
Pending Interrupt[7:0]
Bit 4
Interrupt Enables[7:0]
Interrupt Enables[7:0]
Interrupt Enables[7:0]
Interrupt Enables[7:0]
Interrupt Enables[7:0]
XIO
Drive Mode 0[7:0]
Drive Mode 1[7:0]
Drive Mode 0[7:0]
Drive Mode 1[7:0]
Drive Mode 0[7:0]
Drive Mode 1[7:0]
Drive Mode 0[7:0]
Drive Mode 1[7:0]
Drive Mode 0[7:0]
Drive Mode 0[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
USB SOF
Endpoint7
Endpoint7
USB SOF
Timer0
Timer0
Bit 3
USB Bus Rst Timer2
Endpoint6
Endpoint6
USB Bus
Reset
TrueTouch
TrueTouch
Carry
Bit 2
Endpoint5
Endpoint5
Timer2
Page Bits[2:0]
Page Bits[2:0]
Page Bits[2:0]
Page Bits[2:0]
Page Bits[2:0]
Analog
Analog
Bit 1
Zero
Timer1
Endpoint4
Endpoint4
Timer1
ENSWINT
V Monitor
V Monitor
Bit 0
GIE
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : FF
RW : 00
RW : FF
RW : 00
RW : FF
RW : 00
RW : FF
RW : 00
RW : 00
RW : 00
RW : 00
Access
RC : 00
RL : 02
RW : 0
RW : 0
RW : 0
RW : 0
RW : 0
RW : 0
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