CY8CTMG200-16LGXIT Cypress Semiconductor Corp, CY8CTMG200-16LGXIT Datasheet - Page 175

• Manufacturer Part Number: CY8CTMG200-16LGXIT
• Description: IC MCU 32K FLASH 16-COL
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG200-16LGXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 13
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.3.8
The Endpoint Count Register 1 (EPx_CNT1) sets or reports
the number of bytes in a USB data transfer to the non-con-
trol endpoints.
Bit 7 to 0: Data Count. These bits are the eight LSb of a
9-bit counter. The MSb is the Count MSb bit of the
EPx_CNT0 register. The 9-bit count indicates the number of
data bytes in a transaction. For IN transactions, firmware
loads the count with the number of data bytes to be transmit-
ted to the host. Valid values are 0 to 256. The 9-bit count
also sets the limit for the number of bytes that are received
for an OUT transaction. Before an OUT transaction is
received for an endpoint, this count value must be set to the
maximum number of data bytes to receive. If this count
value is set to a value greater than the number of bytes
(Data + CRC) received, both the data from the USB packet
and the two-byte CRC are written to the USB's dedicated
SRAM.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Address
0,41h
0,43h
0,45h
0,47h
0,49h
0,4Bh
0,4Dh
0,4Fh
EP1_CNT1
EP2_CNT1
EP3_CNT1
EP4_CNT1
EP5_CNT1
EP6_CNT1
EP7_CNT1
EP8_CNT1
EPx_CNT1 Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Data Count[7:0]
Data Count[7:0]
Data Count[7:0]
Data Count[7:0]
Data Count[7:0]
Data Count[7:0]
Data Count[7:0]
Data Count[7:0]
If the number of data bytes received is exactly the same as
the 9-bit count, then only the data is updated into the USB
SRAM and the CRC is discarded but the OUT transaction is
completed according to the Mode bits of the EPx Control
Register. If the number of data bytes received is more than
the 9-bit count, then the OUT transaction is ignored.
After the OUT transaction is complete, the full 9-bit count is
updated by the SIE to the actual number of data bytes
received by the SIE plus two for the packet's CRC. Valid val-
ues are 2 to 258.
To get the actual number of bytes received, firmware must
decrement the 9-bit count by two.
For additional information, refer to the
on page
Bit 3
202.
Bit 2
Bit 1
EPx_CNT1 register
Bit 0
Full-Speed USB
Access
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
175
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