CY8CTMG200-16LGXIT Cypress Semiconductor Corp, CY8CTMG200-16LGXIT Datasheet - Page 64

• Manufacturer Part Number: CY8CTMG200-16LGXIT
• Description: IC MCU 32K FLASH 16-COL
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG200-16LGXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 13
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.3
The following registers are associated with the Internal Main Oscillator (IMO). The register descriptions have associated reg-
ister tables showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not
detailed in the register descriptions that follow. Always write reserved bits with a value of ‘0’. For a complete table showing all
oscillator registers, refer to the
7.3.1
The Internal Main Oscillator Trim Register (IMO_TR) manu-
ally centers the oscillator's output to a target frequency.
This register is loaded with a factory trim value at boot.
When changing frequency ranges, the matching frequency
trim value must be loaded into this register.
7.3.2
The Internal Main Oscillator Trim Register 1 (IMO_TR1)
adjusts the IMO frequency .
Bits 2 to 0: Fine Trim[2:0]. These bits provide a fine tun-
ing capability to the IMO trim. These three bits are the 3 LSB
of the IMO trim with the IMO_TR register supplying the 8
MSB. A larger value in this register will increase the speed
Internal Main Oscillator (IMO)
64
1,E8h
1,FAh
Address
Address
IMO_TR
IMO_TR1
Register Definitions
IMO_TR Register
IMO_TR1 Register
Name
Name
Bit 7
Bit 7
Summary Table of the Core Registers on page
Bit 6
Bit 6
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Bit 5
Bit 5
Bit 4
Bit 4
A TableRead command to the Supervisory ROM returns the
trim values to the SRAM.
page 36
tings stored in Flash tables. Firmware needs to read the
right trim value for desired frequency and update the
IMO_TR register. The IMO_TR register must be changed at
the lower frequency range setting.
For additional information, refer to the
page 281
of the oscillator. The value in these bits varies the IMO fre-
quency: approximately 7.5 kHz/step. When the EnableLock
bit is set in the USB_CR1 register, firmware writes to this
register are disabled.
For additional information, refer to the
page
Trim[7:0]
286.
Bit 3
has information on the location of various trim set-
Bit 3
24.
Bit 2
Bit 2
Fine Trim[2:0]
EraseAll Parameters (05h), on
Bit 1
Bit 1
IMO_TR1 register on
IMO_TR register on
Bit 0
Bit 0
RW : 00
Access
Access
RW : 0
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