CY8CTMG200-16LGXIT Cypress Semiconductor Corp, CY8CTMG200-16LGXIT Datasheet - Page 130

• Manufacturer Part Number: CY8CTMG200-16LGXIT
• Description: IC MCU 32K FLASH 16-COL
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG200-16LGXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 13
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.4
15.4.1
Figure 15-6
vides the baud rate selections. When the block is disabled, all internal state is held in a reset state. When the Enable bit in the
I2C_CFG Register
ple divider are selectable (/2, /4, /8) from the clock rate bits in the
selected, that clock is resynchronized to SYSCLK. The resulting clock is routed to all of the synchronous elements in the
design.
15.4.2
Figure 15-7
sampling, N=4; for 32 times sampling, N=12. N is derived from the half-bit rate sampling of eight and 16 clocks, respectively,
minus the input latency of three (count of 4 and 12 correspond to 5 and 13 clocks).
I2C Slave
130
SDA_OUT
CLK CTR
SDA_IN
SCL_IN
CLOCK
SHIFT
Timing Diagrams
illustrates basic input/output timing that is valid for both 16 times sampling and 32 times sampling. For 16 times
illustrates the I
Clock Generation
Basic I/O Timing
SCL
RESYNC CLOCK
BLOCK RESET
is set, the reset is synchronously released and the clock generation is enabled. All three taps from the rip-
Default
I/O WRITE
ENABLE
N
SYSCLK
2
C input clocking scheme. The SYSCLK pin is an input into a three-stage ripple divider that pro-
8
2
8
4
0
Two SYSCLKS to first block clock.
Figure 15-7. Basic Input/Output Timing
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Figure 15-6. I
1
2
. . .
. . .
. . .
. . .
. . .
. . .
2
C Input Clocking
N
I2C_CFG
0
Register. If any of the three divider taps is
1
2
. . .
. . .
. . .
. . .
. . .
. . .
N
0
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